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ARMv8-A 64-bit Architecture
Training
 

Training

Let MindShare Bring "ARMv8-A 64-bit Architecture" to Life for You

This course covers the addition of ARMv8-A 64-bit architecture to the existing ARMv7 32-bit architecture. Examples of processors that implement this 64-bit architecture are the ARM Cortex-A53 and Cortex A57 processors. The courses covers the Instruction Set Architecture (ISA) details.

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All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.


ARM v8-A 64-bit Architecture Course Info

You Will Learn:

  • ARM architecture (ARMv8-A)
  • Support for execution of 32-bit ARMv7-A code
  • 64-bit ISA (registers, instruction set, system instructions, etc)
  • Floating point and Neon
  • Calling conventions
  • Memory and paging
  • Exception and Interrupt handling, and the exception levels
  • Virtualization (Exception Level 2)
  • TrustZone overview (Exception Level 3)
  • Power management
  • Debug

Course Length: 3 Days

Who Should Attend?

This course is aimed at software developers and system architects developing for systems powered by ARMv8-A processors such as Cortex-A53 and Cortex-A57 Processors. It is relevant for operating system development, device drivers, low-level coding and for application software.

Course Outline:

  • Introduction to ARM 64-bit Architecture
  • ARM architecture profiles, what is v8-A
  • v8-A introduction and rational
  • Support for v7 legacy code
    • AArch32 and AArch64 state
    • v7 instruction set changes
      • Deprecation
      • Additional features
  • 64-bit platform architecture overview
    • Sample SoC
    • MP Core
    • Interconnect (ACE or CHI)
      • Coherency and the interconnect
    • Distributed interrupt controller
    • Role of firmware
    • Booting
  • A64 ISA
  • Integer registers
  • Instruction set
    • Integer operations
    • Memory operations
    • Stack
    • System instructions
      • System control registers
      • Relationship to v7 support and co-processors
    • Calling conventions
    • Memory access (DRAM and device)
      • Ordering model
      • Barriers
        • dmb, dsb, isb
        • load-acquire and store-release
        • Domains
      • Semaphores
      • Cache management
    • Floating point, advanced SIMD, crypto
      • Registers and instructions
    • Exception levels
      • The 4 exception levels
      • Stack model, handler and thread
      • Vector table
      • Core implementation choices
      • Switching AArch32 and AArch64 state
    • Exception and interrupt handling
      • Control of delivery of exceptions and interrupts
      • Syndrome registers
      • Switching exception levels
      • Return from exception
    • Paging
      • Page tables
      • 4K and 64K granules
      • Page sizes
      • TLB management
  • Virtualization Overview
    • Processor virtualization features
    • Interrupt virtualization features
    • Memory management
      • Second level page tables
      • I/O MMU (SMMU)
  • Caches
    • Hardware cache coherency
    • Software responsibilities
    • Cache control in software
  • Security (TrustZone)
    • 32-bit or 64-bit TrustZone
    • Implications on exception levels
    • Switching bitness of TrustZone
  • Other topics
    • Core power management, external power controller
      • Power modes (dormant, shutdown)
      • WFI, WFE, SEV
    • Debug

Recommended Prerequisites:

Knowledge of ARM 32-bit v7 Architecture.

Supplied Materials:

Students will be provided with an electronic version of the slides used in class.