ERRATA
Pentium® Processor System Architecture, 2nd Edition

• On page 62, 2nd table row, 2nd column, should read "...this cache knows that no other."
• On page 116 the section entitled "Flush Acknowledge Special Cycle" line 6 — "Note that the flush acknowledge special cycle........" Delete the word "acknowledge."
• On page 125 all instances of PCI in Table 5-12 should be changed to PWT.
• On page 229 the "I/O Instruction Restart" slot should be deleted from Figure 9-4.
• On page 230 the section entitled "Auto-Halt Restart" second bullet, line 4 — "change bit 0 to a 1 causing......." Replace "1" with "0."
• On page 232 bullets 6 and 7 refer to CR0. Replace CR0 with Eflags.
• On page 233,1st paragraph, 2nd line, should read "...are disabled because."
• On page 241, Figure 10-5, bit 3 is PWT (Page Write-Through), bit 4 is PCD (Page Cache Disable), bit 6 is D (Dirty), bits 11:9 are available for OS use, and bits 21:12 are reserved.
• On page 241, the description of the VM86 extensions was written while the information was still under non-disclosure and was written based on speculation. While close, it's not correct as written. The correct description can be found in our Pentium Pro System Architecture book.
• On page 247, the subject of Protected Mode Virtual Interrupts was under non-disclosure at the time the book was written. The correct description can be found in our Pentium Pro System Architecture book
• On page 247, 1st bulleted item, "NPB" should read "NBP".
• On page 286 output pin D/P# is missing from illustration.
• On page 299, both bulleted items are missing closing parentheses just before "--".
• On page 300, 1st paragraph, 4th line, should read "...just as a single Pentium...".
• On page 303 line 4 reads, "back-to-back writes ..." It should read "back-to-back I/O writes."
• On page 314 Scenario Two should read as follows: "MRM is performing a write that misses its internal data cache. This causes the MRM to perform an external write to the L2 cache. While the write-through is being performed, another bus master begins a memory write cycle to system memory. In this example assume that the following conditions exist: the MRM is performing a memory write that hits the L2 cache; the LRM has a copy of the target line that the MRM is writing to the L2 cache; the target line is stored in LRM's data cache in the M state. A bus master then starts a write to system memory. The LRM also has a copy of the target line (different from the line just hit due to the private bus snoop) that the bus master is writing to in system memory. The line is also stored in the LRM's data cache in the M state. The steps that follow describe the resulting actions:
1. The MRM asserts ADS# at the beginning of the memory write transfer and the LRM detects the write, latches the line portion of the address (A31:A5) and performs the lookup.
2. The LRM's cache lookup results in a snoop hit to a modified line, and the LRM asserts the PHIT# and PHITM# signals to inform the MRM that it is writing to a line containing stale data. The LRM copies the modified line to its "inter-processor snoop" write-back buffer, and the line within the data cache transitions from the M to I state. The LRM also asserts PBREQ# to request bus ownership so that it can perform the write-back.
3. The bus master simultaneously starts a memory write bus cycle to system memory and the L2 cache snoops the address. The L2 snoop hits a line in the M state. It then backs-off the bus master and performs an invalidation cycle (by asserting AHOLD, EADS# and INV=1 and passing the bus master's address) to the processors' local bus.
4. When AHOLD is asserted the MRM floats the address bus. Next, the L2 cache asserts EADS# causing both the MRM and LRM snoop the bus master's address. The LRM detects a snoop hit to a modified line, asserts both PHIT# and PHITM#, and copies the modified line to the "external snoop" write-back buffer. The modified line in the data cache transitions from M to I (because INV=1). Now the LRM has two write-back cycles pending (one resulting from an inter-processor snoop and one from an external snoop).
5. The MRM completes the memory write to the L2 cache, but recognizes that it's overwriting a line containing stale data (a potential source of cache incoherency) and must perform the memory write again once the L2 cache line has been updated by the LRM. Since PBREQ# has been asserted, it grants the buses to the LRM. The MRM and the LRM now change roles.
6. The new MRM starts the external snoop write-back cycle first (because external snoop write-backs take priority over write-backs resulting from inter-processor snoops). The new LRM, still needing to perform the original cache line fill, asserts PBREQ# to regain bus ownership (to perform the memory write transfer again).
7. When the external snoop write-back cycle completes, back-off is released and the bus master is able to complete its write to memory. Next, the MRM performs the inter-processor snoop write-back cycle, without relinquishing control of the buses.
8. When the second write-back completes, the MRM grants the bus to the LRM (the original MRM) by asserting PBGNT# and the processors switch bus ownership back to the original MRM.
9. The MRM restarts the memory write operation.
• On page 321, 1st line under heading should read "This section focuses...".
• On page 321, 2nd paragraph under heading, next to last line, should read "...., allowing any of the 240 entries from 10h to FFh (16d to 255d) to be used by the APIC subsystem.".
• On page 323, last paragraph, next to last line, should read "The local APIC module targeted recognizes, accepts...".
• On page 327, 1st paragraph, 2nd line, reads "Each of these 256-bit registers...", should read "This 256-bit register...".
• On page 327, 3rd paragraph, 2nd line, reads "...delivered to the processor core...", should read "dispatched to the processor core...".
• On page 329, 2nd line, reads "...is updated by the operating system to indicate...", should read "can only be updated by the operating system and indicates...".
• On page 329, last line reads "to interrupt the processor core.", should read "to interrupt the currently-executing program."
• On page 330, add the following clarifying text to the topic at the bottom of the page: "The PPR is automatically loaded (by the APIC) with the same value that the OS loads into the TPR. However, if the APIC receives an interrupt request that beats the threshold in TPR, the APIC interrupts the current task. While the TPR is unaffected, the PPR is automatically changed to reflect the task priority of the interrupt handler now being executed."
• On page 334, item number 2, 3rd line, "chitecture all..." should read "chitectures all...".
• On page 335, item number 4, starting on line 5, should read "An interrupt service routine that is designed to be shared must check to see if its device has an interrupt pending. If so, it executes the service routine. However, if no interrupt request is pending for the device, it jumps...".
• On page 336, table row 2, column 2, "Cycles 2-5 are used arbitrate use of the APIC bus in case more than...", should read "Cycles 2-5 are used to arbitrate for use of the APIC bus in cases where more than...".
• On page 336, table row 3, "...being sent to the processor.", should read "...being sent from the processor.".
• On page 337, 1st bulleted item, should be open parentheses just before "internal...".
• On page 337, paragraph under bulleted list, 3rd line, "For example,...", should read "Just as...".
• On page 337, paragraph under bulleted list, 4th line, now reads "..., and an equivalent...", should read "..., an equivalent...".
• On page 337, Figure 15-10, identify right-most bit as 0 and left-most as 31.
• On page 339, 3rd bulleted item, 2nd line, "...divisor yields...", should read "...divisor and yields...".
• On page 340, 1st paragraph, 5th line, "is illustrated...", should read "are illustrated...".
• On page 341, table row 3, column 2, "0 = active high and 1 = active low..." should read "0 = active high or 1 = active low...".
• On page 341, table row 4, column 2, 4th line, "...low trigger is asserted..." should read "...low trigger level exists...".
• On page 344, Figure 15-15, The rightmost field name currently reads "Status A" should read "Status A1".
• On page 350 the vector description should read, "contains middle of byte of 32-bit execution start address."
• On page 352 the vector description should read, "contains address A11:A4 of the target register location. Also cycles 21 - 36 contain data bits D31:D0 of the target register contents, which are labeled incorrectly in the illustration.
• On page 355, item number 4, 2nd line, "...clock arbitration cycle." should read "...of the clock arbitration cycle.".
• On page 356, 1st paragraph, last line, "...(the winning agents..." should read "...(the winning agent's...".
• On page 357, 2nd paragraph, line 3, reads "...using mechanism." should read "...using this mechanism.".
• On page 363, 2nd bulleted item from bottom of page, 5th line, "Static deliver mode..." should read "Static delivery mode...".
• On page 366, paragraph above item number 1, 1st and 2nd lines, "...reflects the highest priority code currently..." should read "...reflects the priority of code currently ...".
• On page 367, under Focus Processor, add following before 1st sentence "This feature prevents two or more processors from executing the same interrupt hander at the same time." Also amend the paragraph that flows onto the next page to read as follows: "This mechanism is included in case the interrupt vector respective bit is already set in either a local APIC's IRR (indicating its been accepted for servicing, but has not yet been dispatched to the processor) or ISR (indicating that it is currently being serviced) register, meaning that this processor is the focus of this interrupt. This ensures that another processor does not execute an interrupt handler that is already executing in (or will soon be executed by) another processor. The focus processor accepts the interrupt without regard to task priority. Note that the APIC contains a 2-bit buffer for each IRR bit so it can "remember" an additional request that was accepted while it was the focus processor."
• On page 369 the vector description should read, "contains the interrupt vector number."