ERRATA
Protected Mode Software Architecture, 1st Edition

• Page 129, figure 9-2, Bits 15:3 should = 0100 1111 0011 0b.
• Page 130, Byte 0 is labeled "3rd byte of limit" should be "1st byte of limit".
• Page 132, figure 9-4, delete the 3 one bits occupying bit positions 3-5.
• Page 149, Figure 10-3, Page Directory Base Adress field should start at bit 12 rather than bit 11. Also on page 149, delete the last sentence in the paragraph immediately above figure 10-3.
  
• Page 209, table, 2nd row, 2nd column, "DPL > CPL" should read "DPL < CPL".
• Page 210, table, 2nd row, 2nd column, "DPL > CPL" should read "DPL < CPL".
• Page 211, figure 12-9, ESP after pushes should be pointing at Error Code, not EIP.
• Page 229, figure 13-4, Page Directory Base Adress field should start at bit 12 rather than bit 11.
• Page 236, caption of figure 13-9 should read "Page Directory Entry (or Page Table Entry) when Page Table (or page) not Present in Memory".
• Page 237, the figure would be improved by changing the "Page Table start address" pointer origin to the Page Directory entry selected by bits 31:22 of the linear address. Similar improvement is achieved by changing the "Memory Page start address" pointer origin to the Page Table entry selected by bits 21:12 of the linear address.
• Page 241, table row 3 reads "11"b should read "10"b.
• Page 248, 2nd paragraph, line 3, "off to the size" should read "off to the side".
• Pages 297-301, the subject of Protected Mode Virtual Interrupts and VM86 mode extensions was under non-disclosure at the time the book was written. The correct description can be found in our Pentium Pro Processor System Architecture book.
• The description of Big Real Mode on page 61 is incorrect. Make the following changes:
  
  2nd paragraph: "segment starting somewhere above 1MB and having a length of 64KB." should read "segment with a base address of zero and a length of 4GB."
  
  2nd paragraph, last sentence should read "This permits the programmer to address any location within the first 4GB of memory space."
  
  Delete the 3rd paragraph.
• Page 120, figure 8-10: "Privilege Level 0 Code Segment" should read "Privilege Level 3 Code Segment.

In addition, two new protected mode features, global pages and the physical address extension, were added in the Pentium Pro processor. A detailed description of these features can be found in our Pentium Pro Processor System Architecture book