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ARM Cortex-M7 Processor eLearning Course

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ARM Cortex-M7 Processor eLearning Course

Instructor(s): Paul Devriendt
Number of Modules: 25
Subscription Length: 90 days

Course Price
$795.00



ARM Cortex-M7 Processor eLearning Course Info

What's Included?

Cortex-M7 eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)

You Will Learn:

  • Architectural Features of the M7 Processor
  • Powerful & Scalable Instruction Set
  • Interrupts and Exceptions
  • System Interface Architecture
  • Caches
  • Memory Model
  • Assembler Programming intro
  • Debug Features / Techniques

Course Outline:

  • Module 1: Introduction to ARM
    ARM the company, ARM the community, processor portfolio, example ARM-based system, evolution of ARM architecture, ARMv7 vs. ARMv8
  • Module 2a: ARM Cortex-M7 Overview
    Block diagram, architectural features, Micro-architectural features, Scalable instruction set, Core register set, Modes, privilege and stacks
  • Module 2b: ARM Cortex-M7 Overview
    Memory map-1, Memory map-11, Memory interfaces, Tightly Coupled Memory, DMA Interface, AXI Master, cache overview, pipeline features, interrupts & exceptions, memory protection unit (MPU), power management, system timer, core debug, floating-point unit, implementation options, documentation
  • Module 3: ARMv7-M Programmer’s Model
    ARMv7-M profile overview, data types, Integer register set, program counter, link register, stack pointer, program status registers, special purpose registers, Cortex-M4 FP extension registers, privileged execution, stacks, exception handling, instruction set support & examples, reference material, binary upwards compatibility
  • Module 4: Tools Overview for ARM Microcontrollers
    Keil Microcontroller Development Kit (MDK): (uVision IDE, ARM Compiler, µVision Debugger), ULINK Debug Adapters, Keil Development Boards, DS-5 Professional at a Glance, Fast Models from ARM, ARM tools licensing, References, Legacy Tools: RealView Development Suite (RVDS), RVT, RVT2, MPS
  • Module 5: Cortex Microcontroller Software Interface Standard
    Introduction to CMSIS, CMSIS structure, CMSIS bundle and documentation, SMSIS partners, CMSIS-CORE, Using CMSIS-CORE: Instruction access, DSP/SIMD instructions, special register access, NVIC access, system and clock configuration, SysTick access, debug access, CMSIS-DSP: public header file, pre-processor macros, CMSIS-RTOS: API structure (RTX), quick reference, CMSIS-SVD: web infrastructure, file description, XML, validation, CMSIS-Pack: packet description, CMSIS-Driver: functions, example function, CMSIS-DAP: benefits
  • Module 6: Cortex-M7 Processor Core
    M7 Processor Block Diagram, Processor Pipeline (pipeline features, Instruction Issue 1, Instruction Issue 2, Dual-issue 1, Dual-issue 2), Execution Pipelines (ALU, MAC pipeline, Divide unit), Load/Store pipeline 1, Load/Store pipeline 2, Branch pipeline, FPU pipeline, Instruction retire, Prefetch Unit (PFU), Branch Target Address Cache, Branch resolution, Memory Mapped Registers, CPUID Base Register
  • Module 7a: Assembler Programming on ARMv7-M Processors
    Introduction: background, Why is assembler needed, Assembly programming, instruction set basics, Unified Assembler Language (UAL), Thumb instruction encoding choice, example assembly file, Data Processing Instructions: examples, shift operations, rotate operations, flexible second operand (Register and constants), loading constants into variables, multiply, divide, bit manipulation, Quiz and Answers
  • Module 7b: Assembler Programming on ARMv7-M Processors
    Load/Store Instructions: single/double register data transfer, addressing memory, pre/post indexed addressing, multiple regs data transfer, stacks, Quiz and Answers, Flow Control: branch instructions, branch with link, compare & branch on zero, If-Then block, table branch, condition codes/flags, branch ranges, supervisor call, Quiz, Miscellaneous: Byte reversal and CLZ, special-purpose, registers, exclusive access instructions, power management instructions, Quiz, reference materials, Appendix: Thumb-2 improvements, converting legacy assembler
  • Module 8: ARMv7-M Memory Model
    Introduction, Memory Address Space: system address map, system & memory segments, address map overview, private peripheral bus, system control space/block, Memory Types/Attributes: memory types/properties, Alignment/Endianness, effects of endian configuration, types of memory barriers, types of caching technologies and restrictions
  • Module 9a: Cortex-M7 Level 1 Sub-Systems
    Cortex-M7 processor block diagram, Private Peripheral Bus L1 sub-system regions, Register addresses, caching fundamentals, L1 memory system buffers and store buffer, Cache EEC-overview, Point of coherency/unification
  • Module 9b: Cortex-M7 Level 1 Sub-Systems
    Collection of registers: cache level ID, size ID/selection regs, config and control, cache control, auxiliary control, instruction/data error bank regs, cache maintenance, cache initialization and enabling, Tightly Coupled Memory: features, registers and timing, Cache System Considerations.
  • Module 10a: ARMv7-M Exception Handling
    Exception Architecture Overview: exception architecture in ARMv7-M different from other ARM architectures, micro-coded interrupt mechanism, Exception Model: exception types, processor modes can change with exception, external interrupts, pre-emption, exception handling example, ARMv7-M Vector table, reset and exception behavior, Exception Entry and Exit: exception states, exception entry behavior, stacking on exception entry, return address values, exception return, NMI exception entry/return examples, nesting example, tail-chaining example, late-arrival example, exceptions during state restore, Priority Boosting/Instructions: group-/sup-priority selection, interrupt control, status, pending, enable, priority and active registers
  • Module 10b: ARMv7-M Exception Handling
    Interrupt Sensitivity: pulse-sensitive interrupts - single and multiple pulses, level-sensitive interrupts, same interrupt pending, Vector Table and Interrupt Handlers: CMSIS-CORE vector table, writing interrupt handlers, interrupt management, Internal Exceptions & RTOS support: SysTick timer, System Service Call and handlers, priority escalation, internal interrupt registers
  • Module 10c: ARMv7-M Exception Handling
    Fault Exceptions: fault escalation and handling, lockup state and behavior, precise and imprecise exceptions, Cortex-M Profile Feature Comparison: vector table in C, configuration & control register
  • Module 11a: ARMv7-M C/C++ Complier Hints and Tricks
    Basic Compilation, language support, variable compilers supported, optimization levels, architecture/processor selection, Compiler Optimizations: automatic optimizers, tail-call optimization, Instruction scheduling, idiom recognition, inlining functions and example
  • Module 11b: ARMv7-M C/C++ Complier Hints and Tricks
    Loop Transformation, branch target optimization, multifile compilation, Coding Considerations: register usage, parameter passing, loop termination, division operations, compile-time constants, modulo arithmetic, floating point, floating point linkage/examples, C++ support, Mixing C/C++ and Assembler: calling assembly from C/C++, CMSIS, Intrinsics, named register variables, embedded/inline assembler, Variable Types: unaligned accesses, global data, packing of structures, Optimization of memcpy(), base pointer optimization, Quiz
  • Module 12: ARMv7-M Linker and Libraries, Hints and Tips
    Linking Basics: What Linkers Do and how they do it, Object File Structure, Library Structure, Scatter-loading, User and System Libraries: Libraries Versus Object Files, linker library searching, creating and maintaining libraries, Veneers: branches, linker generated veneers, minimizing veneers, Stack Issue: protecting and measuring stack usage, Linker Optimizations and Diagnostics, unused section elimination, RW data compression, small function inlining, linker, linking specific target, debug issues & build time, useful linker diagnostics, ARM Supplied Libraries: ARM compiler standard libraries, microlib, references
  • Module 13: ARMv7-M Synchronization
    Introduction to Synchronization and Semaphores: the need and race for atomicity, critical sections, Exclusive Accesses: effective atomicity, LDREX and STREX instructions, example: lock() and unlock, Programs must be smart, Example of Multi-thread mutex, non-coherent multiprocessor, memory attributes, context switching, exclusive reservation granule, multiprocessor mutex, Bit-banding, Appendix: ARM7-M synchronization primitives, ARMv7-M memory barrier Requirements
  • Module 14: Embedded Software Development for Cortex-M Processors
    Embedded Development Process: default memory map, default C library and initialization, System Startup: reset and initialization, CMSIS startup and initialization, vector table, exception handlers, C Library Initialization, Tailoring the image memory map to target: custom memory map, scatter loading, Linker Placement Rules: ordering objects in scatter file, root regions, Stack and Heap Management: run-time memory management, stack and heap setup, retargeting user setup stackheap, More Memory Map Considerations: process stack pointer setup, MPU initialization, memory-mapped registers, unused sections and entry points, long branch veneers, Post Startup Initialization: extending functions, 8-byte stack alignment in handlers, change thread mode to unpriviledged, Tailoring C Library to Target: thumb C libraries provided, retargeting C library, avoiding C library semihosting, Building and Debugging Your Image: debugging ROM images, Quiz, references
  • Module 15a: ARM7-M Debug
    Introduction to Debug: basic debug requirements and features, invasive and non-invasive debug, private peripheral bus regions, debug register support, CoreSight & Debug Access Port Overview: what is CoreSight, example CoreSight system, debug access port (DAP), Cortex-M3/M4 debug elements, Debug Events: debug states, event sources, halting debug mode, breakpoints vs watchpoints, vector catch, semihosting, 3 resets, downloading boot code, Flash Patch and Breakpoint Unit (FPB): FPB example, FP remapping support
  • Module 15b: ARM7-M Debug
    Data Watchpoint and Trace Unit (DWT): halting debug and examples, trace and profiling, PC sampling register, event counters, cycle counter, Instrumentation Trace Macrocell (ITM): Cortex-M7 and ITM block diagram, stimulus port registers, control and setup, example - MP3 player control processor, Embedded Trace Macrocell (ETM): ETM-M3 and ETM-M4, ETM-M7, instruction trace operation, ETM-M7 block diagram, ETM sharing, Trace Port Interface Unit (TPIU), Trace Packets, Timestamping & Trace Bandwidth: TPIU interface/serial wire output, Quiz
  • Module 15c: ARM7-M Debug
    Implementation Details: Cortex-M7 debug interface, Cortex-Mx or CoreSight SoC-400 DAP, ROM tables and examples, Cortex-M3/M4/M7 debug access port, trace options, Cortex-M7 TPIU block diagram, ETM data trace requirements, off-chip traceclk, Appendix: CoreSight & DAP overview, debug halting control and status register, status bits, fault status register, core registers, debug exception & monitor control register, debug processor registers accessed while processor it halted, debug monitor mode, FlashPatch control and comparator registers, DWT block diagram, data watchpoint control, DWT comparator & mask registers, DWT function registers, ITM & DWT packets, Types of Packets: time-stamping, ITM software trace, DWT trace, exception tracing, instruction trace, branch, hardware event types, synchronization, Cross triggering
  • Module 16: ARM7-M Memory Protection
    Memory Protection Overview: memory protection, system address map, ARMv7-M supports a protected memory system architecture, memory protection unit, Memory Regions Overview: region attribute control, normal memory cacheable properties, Region Overlapping Overview: region overlap examples, sub-regions and examples, Setting Up the MPU Register Types, type, control, region number, region base address, region attribute & size, alias support, Configuring an MPU Region: enabling the MPU, Appendix: ARMv7-M & ARMv6-M MPU comparison, address map overview, CMSIS MPU initialization example, MPU initialization optimization, memory management faults
  • Module 17: ARM7-M Debug Extensions
    Extensions Overview: Cortex-M extensions, DSP extension overview, SIMD instructions, SIMD comparisons, saturating arithmetic, ASX instruction, SIMD multiplies, Floating Point Extension Overview: FPU enabling, Floating-point Status and Control Register, floating-point exceptions, floating-point instructions, exception handling, extended stack frame, lazy context save
Course Modules
ModuleLength
Module 1: ARM Cortex-M7 Intro22 minutes
Module 2a: ARM Cortex-M7 Overview19 minutes
Module 2b: ARM Cortex-M7 Overview25 minutes
Module 3: ARMv7M Programmer's Model40 minutes
Module 4: Tools Overview For ARM Microcontrollers15 minutes
Module 5: Cortex Microcontroller Software Interface Standard23 minutes
Module 6: Cortex-M7 Processor Core50 minutes
Module 7a: Assembler Programming on ARMv7-M Processors31 minutes
Module 7b: Assembler Programming on ARMv7-M Processors38 minutes
Module 8: ARMv7-M Memory Model44 minutes
Module 9a: Cortex-M7 Level 1 Sub-Systems36 minutes
Module 9b: Cortex-M7 Level 1 Sub-Systems27 minutes
Module 10a: ARMv7-M Exception Handling20 minutes
Module 10b: ARMv7-M Exception Handling34 minutes
Module 10c: ARMv7-M Exception Handling31 minutes
Module 11a: ARMv7-M C/C++ Complier Hints and Tricks22 minutes
Module 11b: ARMv7-M C/C++ Complier Hints and Tricks52 minutes
Module 12: ARMv7-M Linker and Libraries, Hints and Tips30 minutes
Module 13: ARMv7-M Synchronization27 minutes
Module 14: Embedded Software Development for Cortex-M Processors47 minutes
Module 15a: ARM7-M Debug23 minutes
Module 15b: ARM7-M Debug26 minutes
Module 15c: ARM7-M Debug25 minutes
Module 16: ARM7-M Memory Protection31 minutes
Module 17: ARM7-M Debug Extensions15 minutes