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Comprehensive ARM Architecture eLearning Course

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Comprehensive ARM Architecture eLearning Course

Instructor(s): Paul Devriendt
Number of Modules: 28
Subscription Length: 90 days

Course Price
$995.00



Comprehensive ARM Architecture eLearning Course Info

What's Included?

ARM eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)

Benefits of eLearning:

  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course

You Will Learn:

  • ARM architecture: ARMv7 (32-bit) and ARMv8 (64-bit) architectures, along with some of the history
  • ARM microarchitecture, the internals of some of the different processors comprising the Cortex family
  • Comparisons and contrasts with the Intel IA-32 architecture and microarchitectures
  • Buses connecting the processor core(s) to the rest of the system
  • Numerous examples of how this is used in SoC (System on a Chip) designs
  • The ARM business and licensing model, and how this leads to a variety of devices

Course Outline:

  • Module 1: ARM Overview
    - Intro to ARM the company, RISC vs CISC, ARMv7 vs v8, Architecture Profiles (-A, -R, -M), Intro to SoCs
  • Module 2: v7 Architecture Introduction
    - Overview of v7 instruction sets and extensions, compatibilities and incompatibilities
  • Module 3: v7 Integer Registers
    - Application registers, PC (r15), APSR, Register Banking
  • Module 4: v7 Instructions - ARM
    - Three register format, Immediates, Shifts, Multiply and Accumulate, Divide, Moves and Returns, Branch, Branch and Link, Instruction Format, Condition Codes
  • Module 5: v7 Instructions - Thumb and Jazelle
    - Thumb and Thumb2 vs ARM, Low Registers, If Then Else (Conditional Execution), Immediates, Switching Between ARM and Thumb, Jazelle-RCT, Jazelle DBX, ThumbEE
  • Module 6: v7 Instructions - Vector Floating Point / Neon
    - VFPv3 and VFPv4, VFP Registers, Floating Point Types, Advanced SIMD (Neon) Registers, SIMD Data Types
  • Module 7: v7 Memory Accesses
    - Endianness, Alignment, Load/Store Architecture, Stack Usage, Memory Copy, Device Access, Memory Types, Memory Ordering, Barrier Instructions, Shareability Domains, Semaphores, v7-M Bit Banding, v7-M and v7-R Tightly Coupled Memory (TCM)
  • Module 8: v7 Privilege, Mode, State
    - User vs Privileged, v7 TrustZone Extension, Normal vs Secure World, Monitor Mode, v7 Coprocessor Concept, Detecting and Accessing Coprocessors
  • Module 9: v7 Exceptions and Interrupts
    - IRQ vs FIQ, GIC, Exception Table, Exception Tables with TrustZone, Taking an Exception, Returning from an Exception
  • Module 10: v7-M Memory Map and v7-R Memory Protection
    - -M Fixed Memory Map, -R Memory Regions, Memory Access Faults
  • Module 11: v7-A Memory Management (Paging)
    - Paging Concepts, TLBs, Page and Section Sizes (4KB, 64KB, 1MB, 16MB), Table Access (TTBR0 and TTBR1), TLB Maintenance, Page Table Descriptors, Domains, ASIDs
  • Module 12: v7 Large Physical Address Extension (LPAE)
    - Three Level Table Walk, 64-bit Descriptor, Large Pages (2MB and 1GB)
  • Module 13: v7 Hardware Virtualization
    - Hardware Extension vs Software, Trap and Emulate, Banked Registers, HCR, HSR, Virtualization and Paging, Virtualization and Interrupts
  • Module 14: v7 Debug and Analysis Support
    - Performance Monitors, Monitor Mode, Halting Debug Mode, Debug Port, Breakpoints and Watchpoints, Breakpoint Instruction (BKPT), Vector Catch, Trace
  • Module 15: v8 Architecture Introduction
    - AArch64 vs AArch32, Cortex-A57 and A53, 64-bit Virtual Addressing, Instruction and Register Implications, LP64 and LLP64
  • Module 16: v8 Integer Registers
    - 64-bit Registers, ELF ABI Usage, Operation Size Examples, PState, DAIF and Interrupt Control, MRS, MSR and System Registers
  • Module 17: v8 Instructions
    - New Instruction Set, Functionality Changes, Using Condition Flags, Branch and Jump, Return, Conditional Branches and Other Instructions, Immediates and Moves, Bit Manipulation, System Instructions
  • Module 18: v8 Memory Accesses
    - Alignment, Addressing Modes, Load and Store Pair, Non-temporal Pair, Load-Acquire and Store-Release
  • Module 19: v8 Floating Point, Neon and Crypto Extension
    - Floating Point Registers and Types, Advanced SIMD Registers and Types
  • Module 20: v8 Exceptions and Interrupts
    - Exception Levels (EL0, EL1, EL2, EL3), Secure State, Taking an Exception, Transitions Between 32-bit and 64-bit, Vector Table
  • Module 21: v8 Memory Management (Paging)
    - 64-bit Virtual Addressing, Address Size, Mapping and Translation based on Exception Level, Page Sizes (4KB, 64KB, 2MB, 1GB)
  • Module 22: Caches
    - Cache Line, Way, Tag, Cache Line State (MESI, MOESI, MESIF), Management of Coherency, Cortex-A9 Caches, Cache Prefetch Hints, Cache, TLB and Branch Prediction, Cache and TLB Maintenance (v8)
  • Module 23: Pipelines: Cortex-M and Cortex-R4
    - Cortex-M0/1 Pipeline, Cortex-M4 Pipeline, Cortex-R4 Pipeline
  • Module 24: Pipelines: Cortex-A8 / A9 / A5
    - Cortex-A8 Pipeline, Caches and more; Cortex-A9 Pipeline, Caches and more; Cortex-A5 Pipeline, Caches and more
  • Module 25: Pipelines: Cortex-A15 / A57 / A7 / A12
    - Cortex-A15 Pipeline, Caches and more; Cortex-A57 Pipeline, Qualcomm Krait (Snapdragon s4), Cortex-A7 Pipeline, Cortex-A12 Pipeline
  • Module 26: AMBA: AXI 3, APB and PCIe Bridges
    - SoC Interconnects, AMBA Versions, AXI Master and Slave Channels, AXI Transaction Types, APB Bridge to Slave, APB Transaction Examples, AXI to PCIe Bridge
  • Module 27: AMBA 4 ACE, big.LITTLE and AMB5
    - Coherence Channels, ACE Transaction Types, ACE Lite, AMB5 Coherent Hub Interconnect (CHI), Server Soc Interconnect Considerations
  • Module 28: Power Management, Embedded Issues, Tools and Support
    - Platform Power Management, Cortex-A9 Power Modes, WFI, WFE, SEV, Dormant / Shutdown Modes, Core Power Domains, Predictability, Realtime - Interrupt Latency, ARM Supplied Software and Hardware Tools, GNU / Linux / Android / Microsoft and ARM, Real Time OS Considerations, Linaro

A La Carte Options

We're pleased to announce that we also offer the option to customize your own course by purchasing only the modules you need. Expand this section to view the specific topics available. Each topic can be purchased separately, or you can purchase the entire comprehensive course.

Course Modules
ModuleLength
Module 1: ARM Overview48 minutes
Module 2: v7 Architecture Introduction32 minutes
Module 3: v7 Integer Registers34 minutes
Module 4: v7 Instructions - ARM42 minutes
Module 5: v7 Instructions - Thumb and Jazelle32 minutes
Module 6: v7 Instructions - Vector Floating Point / Neon20 minutes
Module 7: v7 Memory Accesses65 minutes
Module 8: v7 Privilege, Mode, State33 minutes
Module 9: v7 Exceptions and Interrupts47 minutes
Module 10: v7-M Memory Map and v7-R Memory Protection21 minutes
Module 11: v7-A Memory Management (Paging)57 minutes
Module 12: v7 Large Physical Address Extension (LPAE)14 minutes
Module 13: v7 Hardware Virtualization34 minutes
Module 14: v7 Debug and Analysis Support28 minutes
Module 15: v8 Architecture Introduction31 minutes
Module 16: v8 Integer Registers54 minutes
Module 17: v8 Instructions50 minutes
Module 18: v8 Memory Accesses17 minutes
Module 19: v8 Floating Point, Neon and Crypto Extension11 minutes
Module 20: v8 Exceptions and Interrupts28 minutes
Module 21: v8 Memory Management (Paging)18 minutes
Module 22: Caches50 minutes
Module 23: Pipelines: Cortex-M and Cortex-R417 minutes
Module 24: Pipelines: Cortex-A8 / A9 / A542 minutes
Module 25: Pipelines: Cortex-A15 / A57 / A7 / A1255 minutes
Module 26: AMBA: AXI 3, APB and PCIe Bridges53 minutes
Module 27: AMBA 4 ACE, big.LITTLE and AMB539 minutes
Module 28: Power Management, Embedded Issues, Tools and Support35 minutes