Comprehensive PCI Express 3.1 eLearning Course

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Comprehensive PCI Express 3.1 eLearning Course

Instructor(s): Mike Jackson
Number of Modules: 31
Subscription Length: 90 days

Course Price
$995.00
Bundle Price (Course & Arbor)
$1,395.00
(more info on Arbor)



Comprehensive PCI Express 3.1 eLearning Course Info

What's Included?

PCI Express 3.1 eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)
PCI Express eBook
(yours to keep, does not expire)

Benefits of eLearning:

  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course

You Will Learn:

  • PCI Express features and capabilities
  • The definition and responsibilities of each of the layers in the interface
  • How hardware-based automatic error detection and correction mechanism works
  • The various additional levels of error detection and reporting
  • The details of the packet-based protocol used by PCIe
  • The address space and packet-routing methods used
  • How the various power management techniques work
  • Configuration register details that provide control and status visibility to software
  • What are some ECNs related to PCI Express 2.1 and 3.1 specification
  • What changes are needed to run the link at 8.0GT/s (rev 3.0 speeds)


MindShare's PCI Express System Architecture course starts with a high-level view of the design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.

Who Should View?

This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers.

Course Outline:

  • Module 1: PCIe Background Info
    - PCI and PCI-X basics that carry forward to PCI Express
  • Module 2a: PCIe Overview
    - High level overview of PCIe; Component types, device layers, transaction types, etc.
  • Module 2b: PCIe Overview
    - High level overview of PCIe; Component types, device layers, transaction types, etc.
  • Module 3: Configuration Space Overview
    - Basics of config space registers and accessing config space and includes an intro to the Arbor software tool
  • Module 4: Address Space and Transaction Routing
    - Covers the behavior and programming of BARs and Base and Limit registers as well as routing methods in a PCIe system
  • Module 5: TLP Elements
    - Discusses all TLP types and the header fields for each (memory, IO, config, messages, etc.)
  • Module 6: Flow Control
    - Protocol of flow control including credit values and frequency of transmission
  • Module 7: Quality of Service
    - Traffic classes, virtual channels, and arbitration schemes
  • Module 8: Transaction Ordering
    - Ordering rules
  • Module 9: DLLP Elements and Ack/Nak Protocol
    - Coverage of Ack/Nak state-machine and example scenarios
  • Module 10a: Physical Layer: Logical (2.5 and 5.0GT/s)
    - Transmit side: Byte striping, scrambling, 8b/10b, SerDes
  • Module 10b: Physical Layer: Logical (2.5 and 5.0GT/s)
    - Receive (Rx) side: CDR, Elastic Buffer, SKP ordered-sets, Lane-to-lane deskew, 8b/10b decoding
  • Module 11: Physical Layer: Logical (8.0GT/s)
    - Byte striping, scrambling, 128/130b, packet encapsulation
  • Module 12: Physical Layer: Electrical (2.5, 5.0 and 8.0GT/s)
    - High-speed signaling, differential signals, ISI, de-emphasis, equalization, eye diagrams
  • Module 13a: Link Initialization and Training
    - LTSSM(Detect, Polling, Configuration, Recovery), link and lane numbering, speed change
  • Module 13b: Link Initialization and Training
    - Equalization procedure, dynamic link width changes, loopback, etc.
  • Module 14: Interrupts
    - Interrupt messages, MSI, MSI-X
  • Module 15: Error Detection and Handling
    - Correctable, Non-Fatal, and Fatal errors and how they're reported and handled (PCI-compatible, baseline, and advanced error reporting)
  • Module 16a: Power Management
    - Device power states (D0, D1, D2, D3), link power states (L0, L0x, L1, L2, L2/L3 Ready, L3), Active State Power Management (ASPM)
  • Module 16b: Power Management
    - Software power management, power management events (PME), Dynamic Power Allocation (DPA), Optimized Buffer Flush Fill (OBFF), Latency Tolerance Reporting (LTR)
  • Module 17: System Resets
    - Hot, Warm, Cold and Function-Level resets
  • Module 18: Hot Plug and Power Budgeting
    - Hardware elements, software elements, power budgeting
  • Module 19: Overview of 2.1 Changes
    - Overview of: Multicasting, Protocol Multiplexing (PMUX), TLP Processing Hints (TPH), ID-based ordering, Atomic Operations, etc.
  • Module 20: Overview of 3.1 Changes
    - Overview of: Downstream Port Containment (DPC), L1 Substates, Lightweight Notification (LN), Process Address Space ID (PASID), Precision Time Measurement (PTM), Mobile PCIe (M-PCIe), Device Readiness Notifications (DRS), etc.
  • Module 21a: Details of 2.1 Changes
    - Multicasting, Protocol Multiplexing (PMUX), TLP Processing Hints (TPH)
  • Module 21b: Details of 2.1 Changes
    - ID-based ordering, Alternative Routing-ID Interpretation (ARI), Atomic Operations, Internal Error Reporting, Resizable BARs
  • Module 22a: Details of 3.1 Changes
    - Downstream Port Containment (DPC)
  • Module 22b: Details of 3.1 Changes
    - L1 Substates, Lightweight Notification (LN)
  • Module 22c: Details of 3.1 Changes
    - Process Address Space ID (PASID), Precision Time Measurement (PTM)
  • Module 22d: Details of 3.1 Changes
    - Mobile PCIe (M-PCIe), Device Readiness Notifications (DRS)
  • Module 23: Arbor Lab Solutions
    - Answers to all the Arbor labs

A La Carte Options

We’re pleased to announce that we also offer the option to customize your own course by purchasing only the modules you need. Expand this section to view the specific topics available. Each topic can be purchased separately, or you can purchase the entire comprehensive course.

Course Modules
ModuleLength
Module 1: PCIe Background Info46 minutes
Module 2a: PCIe Overview55 minutes
Module 2b: PCIe Overview38 minutes
Module 3: Configuration Space Overview47 minutes
Module 4: Address Space and Transaction Routing48 minutes
Module 5: TLP Elements66 minutes
Module 6: Flow Control36 minutes
Module 7: Quality of Service43 minutes
Module 8: Transaction Ordering13 minutes
Module 9: DLLP Elements and Ack/Nak Protocol51 minutes
Module 10a: Physical Layer: Logical (2.5 and 5.0GT/s)49 minutes
Module 10b: Physical Layer: Logical (2.5 and 5.0GT/s)22 minutes
Module 11: Physical Layer: Logical (8.0GT/s)63 minutes
Module 12: Physical Layer: Electrical (2.5, 5.0 and 8.0GT/s)57 minutes
Module 13a: Link Initialization and Training44 minutes
Module 13b: Link Initialization and Training64 minutes
Module 14: Interrupts46 minutes
Module 15: Error Detection and Handling66 minutes
Module 16a: Power Management39 minutes
Module 16b: Power Management35 minutes
Module 17: System Resets12 minutes
Module 18: Hot Plug and Power Budgeting32 minutes
Module 19: Overview of 2.1 Changes23 minutes
Module 20: Overview of 3.1 Changes27 minutes
Module 21a: Details of 2.1 Changes47 minutes
Module 21b: Details of 2.1 Changes20 minutes
Module 22a: Details of 3.1 Changes24 minutes
Module 22b: Details of 3.1 Changes29 minutes
Module 22c: Details of 3.1 Changes21 minutes
Module 22d: Details of 3.1 Changes37 minutes
Module 23: Arbor Lab Solutions24 minutes