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Intel x86 Processor and Platform Architecture eLearning Course

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Intel x86 Processor and Platform Architecture eLearning Course

Instructor(s): Jay Trodden
Number of Modules: 47
Subscription Length: 90 days

Course Price
$995.00
Bundle Price (Course & Arbor)
$1,395.00
(more info on Arbor)



Intel x86 Processor and Platform Architecture eLearning Course

What's Included?

Course eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)
x86 ISA eBook
(yours to keep, does not expire)

Benefits of eLearning:

  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready

Who Should View?

This in-depth course is a "must" for anyone dealing with designing, verifying, validating, debugging, or developing for x86-based platforms. The x86 instruction set architecture and platform architecture have evolved over a period of almost 40 years. This course describes the current architectures but also explains how we got to the current architecture based on the history and decisions made. It doesn't matter whether you're a hardware engineer or a software developer, this course has an enormous amount of relevant info for you.

Course Outline:

  • Module 1: Course Introduction
    - Scope of course, outline, Arbor introduction
  • Module 2: Intel x86 Platform Background
    - Walks through x86 CPU evolution
  • Module 3: Introduction To Platform Examples
    - Describes general characteristics and differences between server platforms, desktop platforms and tablet platforms
  • Module 4: Haswell Core i7-v4 Desktop
    - Discusses high-level CPU features as well as busses off processor package and PCH (PCIe, DMI, Video, USB, HD audio, ethernet, SATA, SPI Flash, SMBus, and more)
  • Module 5: Haswell E5-2600 v3 Server
    - Discusses high-level CPU features and multi-socket systems as well as busses off processor packages and PCH (PCIe, DMI, BMC, USB, HD audio, ethernet, SATA, SPI Flash, SMBus, and more)
  • Module 6: Broadwell Core M SOC Tablet
    - Discusses high-level CPU features and concept of Multi-Chip Package (MCP) as well as general features of tablet platforms
  • Module 7: Broadwell Xeon E7-8800 v4 Server
    - Discusses high-level CPU features and multi-socket systems as well as busses off processor packages and PCH (PCIe, DMI, BMC, USB, HD audio, ethernet, SATA, SPI Flash, SMBus, and more)
  • Module 8: x86 Instruction Set Overview
    - x86 instruction basics, instruction variants, integer operations, floating-point operations, MMX, SSE, AVX, program flow-related instructions, hardware-related instructions, x86 instruction format
  • Module 9: x86 Register Set Introduction
    - Registers per thread (logical processor), general-purpose registers, flags register, x87 registers, MMX registers, XMM registers, YMM registers, ZMM registers, segment registers, control registers, debug registers, model-specific registers (MSRs)
  • Module 10: x86 CPU Operating Modes
    - Real Mode, (legacy) Protected Mode, Virtual-8086 Mode, System Management Mode, Compatibility Mode, 64-bit Mode, Long Mode (IA-32e Mode) vs Legacy Mode
  • Module 11: Platform Addressing
    - Memory space (system memory vs. memory-mapped IO: MMIO), IO space, PCI config space
  • Module 12a: CPU Memory Segmentation Part A
    - Memory accesses, address generation (effective address, logical address, linear/virtual address, physical address), Real Mode segmentation
  • Module 12b: CPU Memory Segmentation Part A
    - Code and Data segment descriptors, Global Descriptor Table (GDT), Local Descriptor Tables (LDTs), descriptor cache, flat memory model, Intel64 segmentation, long bit (CS.L)
  • Module 13a: Paging and TLBs
    - Paging concepts and basic paging implementation in x86 architecture, on-demand paging example
  • Module 13b: Paging and TLBs
    - x86 paging facts and page sizes: 4KB, 2MB, 4MB, 1GB, details of PTE, PDE, PDPE, PML4E, Page Size Extensions (PSE), Physical Address Extensions (PAE), Long Mode paging (Page Map Level 4 - PML4), intro to Processor Context ID (PCID), paging access rights determination, protection keys, execute disable (aka no execute)
  • Module 13c: Paging and TLBs
    - Purpose of Translation Lookaside Buffers (TLBs), TLB behavior, global pages, contents of TLB entry, managing TLBs (INVLPG, INVPCID, INVVPID, MOV CR0, CR3, CR4), TLB shootdowns
  • Module 14: CPU Internal Architecture Overview
    - Package resources per core vs shared, caches, instruction pipeline, local APIC, system agents (L3, power control unit, integrated memory controller, etc.), NUMA introduction
  • Module 15: CPU Microarchitecture
    - Description of pipeline stages, instruction fetch, branch prediction, instruction decode, macro-op and micro-op fusion, uCode ROM, uOp cache, register files, load/store buffers, reorder buffer (ROB - retire order buffer), reservation stations, execution units
  • Module 16: Cache Basics
    - Intro to caching, cache lines, evictions, intro to memory types and assigning of memory types (Memory Type and Range Registers - MTRRs; and Page Attribute Table - PAT)
  • Module 17: CPU Conduct In Cache Regions
    - Behavior when operating in Uncacheable (UC) space, Write Combining (WC) space, Write Through (WT) space, Write Protect (WP) space and Write Back (WB) space
  • Module 18: Cache Hardware Architecture
    - Common structure/layout of L1 Data cache (L1D), L1 Code cache (L1C), L2 cache, L3 (LLC) cache, Data Direct IO (DDIO) behavior
  • Module 19: Cache and Memory QoS
    - Cache Monitoring Technology (CMT), Cache Allocation Technolgy (CAT), Code and Data Prioritization (CDP), Memory Bandwidth Monitoring (MBM)
  • Module 20: Other Cache Topics
    - L4 cache option, non-temporal stores, software prefetch instructions, TLB sizes
  • Module 21: CPU and PCH Interface Overview
    - Overview of key interfaces off processor package and PCH
  • Module 22: Main Memory DRAM
    - Converting from system memory address to Rank (chip select) / Bank / Row / Column, error handling, DDR4 vs DDR3, example DDR transactions
  • Module 23a: QuickPath Interconnect (QPI)
    - QPI intro, packets, flits, phits, coherent vs non-coherent traffic, source snooping protocol, home snooping protocol
  • Module 23b: QuickPath Interconnect (QPI)
    - Home snooping protocol, DMA operations and QPI interaction
  • Module 24: PCI Express (PCIe)
    - PCIe intro, link characteristics, types of devices (Root Complex, Root Complex Port, Switch, Native Endpoint, Legacy Endpoint, Bridge), device layers (Transation Layer, Data Link Layer, Physical Layer)
  • Module 25: PCI Configuration Space
    - PCI configuration space, capability structures, PCI enumeration process
  • Module 26: Interrupts - Intro and Controller History
    - Intro to interrupt handling, hardware interrupts vs software interrupts vs exceptions, interrupt vectors, locating handler via Interrupt Descriptor Table, 8259A interrupt controller basics, intro to APIC / IO APIC and xAPIC
  • Module 27: Interrupts - Local APIC Basics
    - Local APIC registers, x2APIC, priority among hardware interrupts, masking interrupts based on priority threshold (TPR), behavior of local APIC
  • Module 28: Interrupts - Delivery Options
    - APIC IDs (physical APID ID and logical APIC ID), physical destination mode, logical flat destination mode, logical cluster destination mode, redirectable interrupts, power aware interrupt remapping (PAIR)
  • Module 29: Interrupts - MSI, Interrupt Remapping and IPIs
    - Message Signaled Interrupts (MSI), address and data encodings for x86 platforms, setting up MSI info at devices (PCI config space), MSI-X, purpose of interrupt remapping and overview of concept, Inter-Processor Interrupts (IPIs)
  • Module 30a: Overview of Virtualization Support
    - What is virtualization, different approaches (application level vs machine level), software solutions (ring deprivileging, binary translation, paravirtualization), Intel VT-x, virtual machine control structure (VMCS), Intel VT example usage
  • Module 30b: Overview of Virtualization Support
    - Memory and virtualization (shadow page tables vs extended page tables - EPTs), intro to VT-d features (IO virtualization)
  • Module 31: CPU Performance Monitoring
    - Core performance monitoring, performance monitoring counters, fixed function vs general purpose monitoring, precise event based sampling (PEBS), uncore performance monitoring
  • Module 32: Machine Check Architecture (MCA)
    - MCA error detection and reporting, MCA error classes (corrected and uncorrected), MCA-related interrupts, MCA registers, MCA banks
  • Module 33: System Management Mode (SMM)
    - Purpose of SMM, SMRAM, System Management Interrupt (SMI), sources of SMI, SMM handler
  • Module 34: Microcode Update
    - Need for microcode updating, update procedure
  • Module 35: PCH: Internal Architecture
    - Overview of internal blocks within a PCH
  • Module 36: PCH: USB Interface
    - Overview of USB 2.0, USB 3.x and xHCI, USB topologies, hubs
  • Module 37: PCH: SATA Interface
    - Overview of Serial ATA
  • Module 38: PCH: SMBus Interface
    - Overview of System Management Bus
  • Module 39: PCH: SPI
    - Overview of Serial Peripheral Interface
  • Module 40: Platform Power Management
    - ACPI overview (global states, system states, etc.), C-state meaning and transitions, P-state meaning and transitions, Enhanced Intel SpeedStep (EIST), Turbo Boost
  • Module 41: Platform Thermal Management
    - Digital Thermal Sensor, thermal management registers, thermal control circuit (TCC), thermal interrupt, adaptive thermal monitor (ATM), clock modulation, Vcc adjustments, thermal trip, PECI
Course Modules
ModuleLength
Module 1: Course Introduction17 minutes
Module 2: Intel x86 Platform Background16 minutes
Module 3: Platform Information Sources49 minutes
Module 4: Skylake Core i7 v6 Desktop25 minutes
Module 5: Haswell E5-2600 v3 Server13 minutes
Module 6: Broadwell Core M SOC Tablet22 minutes
Module 7: Broadwell Xeon E7-8800 v4 Server13 minutes
Module 8: x86 Instruction Set Overview54 minutes
Module 9: x86 Register Set Introduction52 minutes
Module 10: x86 CPU Operating Modes49 minutes
Module 11: Platform Addressing39 minutes
Module 12a: CPU Memory Segmentation Part A25 minutes
Module 12b: CPU Memory Segmentation Part B56 minutes
Module 13a: x86 Paging and TLBs45 minutes
Module 13b: x86 Paging and TLBs52 minutes
Module 13c: x86 Paging and TLBs53 minutes
Module 14: CPU Internal Architecture Overview44 minutes
Module 15: CPU Microarchitecture38 minutes
Module 16: Cache Basics59 minutes
Module 17: Cache Regions & CPU Conduct58 minutes
Module 18: Cache Hardware Architecture45 minutes
Module 19: Cache and Memory QoS37 minutes
Module 20: Other Cache Topics31 minutes
Module 21: CPU and PCH Interface Overview42 minutes
Module 22: Main Memory DRAM44 minutes
Module 23a: QuickPath Interconnect (QPI)71 minutes
Module 23b: QuickPath Interconnect (QPI)39 minutes
Module 24: CPU PCI Express (PCIe)61 minutes
Module 25: PCI Configuration Space73 minutes
Module 26: Interrupts: Intro and Controller History48 minutes
Module 27: Interrupts: Local APIC Basics38 minutes
Module 28: Interrupts: Delivery Options34 minutes
Module 29: Interrupts: MSIs, Interrupt Remapping and IPIs54 minutes
Module 30a: Overview of Virtualization Support47 minutes
Module 30b: Overview of Virtualization Support32 minutes
Module 32: Machine Check Architecture (MCA)44 minutes
Module 33: System Management Mode (SMM)30 minutes
Module 34: Microcode Update13 minutes
Module 35: PCH Internal Architecture40 minutes
Module 36: Platform USB Interfaces34 minutes
Module 37: Platform SATA Interfaces56 minutes
Module 38: Platform SMBus Interfaces42 minutes
Module 39: Platform SPI Interface17 minutes
Module 40a: Platform Power Management Part A34 minutes
Module 40b: Platform Power Management Part B44 minutes
Module 41: Platform Thermal Management28 minutes