USB 3.1


Let MindShare Bring "Hands-On USB 3.1 with xHCI" to Life for You

Each generation of the USB is backward compatible and a USB 3.1 topology may include devices operating at five speeds. USB 2.0 signals handle three of the data rates: 1.5 Mb/s Low Speed (LS), 12 Mb/s Full speed (FS), and 480 Mb/s High Speed (HS). USB 3.0 added an additional set of signals to USB cables and connectors to support a fourth speed, 5 Gb/s SuperSpeed (SS). USB 3.1 brings the 5th speed option, 10 Gb/s SuperSpeedPlus (SSP). The USB 2.0 and SS/SSP signals are physically separate and USB 3.1 refers to devices operating at LS/FS/HS as being in the USB 2.0 topology; devices operating at SS and SSP are in the Enhanced SuperSpeed (ESS) topology and are also referred to as ESS Gen1 and Gen2.
In addition to the faster data rates, the ESS topology employs protocol optimizations including unicast packets, device asynchronous messages, as well as link level flow control, error handling, and power management.

All generations of USB rely on platform host controllers to manage devices attached to each bus instance. USB 2.0 employed UHCI/OHCI and EHCI compliant host controllers to handle low, full, and high speed devices. The advanced capabilities of USB 3.1 require a new generation of host controller. Course topics include Intel’s eXtensible Host Controller Interface (xHCI). A single host controller based on xHCI can manage both USB 2.0 and Enhanced SuperSpeed topologies as well as attached devices of any USB speed. The xHCI operational model, software interface (registers, memory data structures), doorbell-based work notification, and hardware transaction scheduling are all described.

MindShare's Current Offerings for USB:

Course Name

Virtual Classroom

USB 3.1 with xHCI
4 days

  4 days
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USB Type-C and Power Delivery
1 day

1 day

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USB 3.1 Update
1 day

1 day
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Fundamentals of USB 3.1
1 day

1 day
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Embedded USB 2.0
4 days

4 days

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All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.

USB 3.1 with xHCI Course Info

Course Length: 4 Days

Who Should Attend?

This course is designed with hardware, software, and validation engineers in mind. Features and limitations of each generation of USB are described, as is the role of xHCI compliant host controllers in managing attached devices and hubs.

Course Outline:

Part 1: USB 3.1

  • Introduction to USB 3.1
    • USB 3.1 Motivation
    • USB Background
    • USB 3.1 New Feature Summary
  • ESS End-to-End Protocol
    • Role of the Host Controller
    • Introduction to Protocol Layer Packets
      • Transaction Packets (TPs)
      • Data Packets (DPs)
      • Isochronous Timestamp Packet (ITP)
      • Link Management Packet (LMPs)
      • Five Packets for IN/OUT Transactions
    • Gen 1 IN/OUT Transactions
      • Gen 1 Packet Formats
      • Bulk Transfers
      • Control Transfers
      • Interrupt Transfers
      • Isochronous Transfers
    • Gen 2 IN/OUT Transactions
      • Gen 2 Packet Differences
      • Gen 2 Transfer Differences
  • USB 3.1 Hubs
    • USB 3.1 Hub Overview
    • Gen 1 Upstream Link
    • Differences if Upstream Link is Gen 2
  • ESS Port-to-Port Protocol
    • Gen 1 Port to Port Protocol
      • LTSSM and ESS Link States
      • Link Traffic Overview
      • Header Packet Processing
      • Header Packet Flow Control
      • Packet Acknowledgement and Retry
    • Gen 2 Port to Port Protocol Differences
      • Link Traffic
      • Header Packet Processing
      • Header Packet Flow Control
  • ESS Chip-to-Chip Protocol
    • Gen 1 Physical Layer Logic
    • Gen 2 Physical Layer Logic Differences
  • ESS Link Reset Events
  • ESS Link Training
    • Gen 1 Link Training
    • Gen 2 Link Training Differences
  • Link Recovery and Retraining
    • Gen 1 Link Recovery
    • Gen 2 Link Recovery Differences
  • Enumeration and Configuration
    • Device Configuration
    • Hub Configuration
    • Accessing and Viewing Descriptors
  • ESS Power Management
    • Introduction
    • ESS Link Power Management
    • Software Role
    • Handshake Sequence
    • Function Suspend
    • Latency Tolerance Message (LTM) Reporting

Part 2: eXtensible Host Controller Interface (xHCI) for USB

  • Overview of xHCI
    • Motivations and Goals
    • Dual Bus Topology
    • xHCI Implementation Options
    • Root Hub Ports
  • xHCI Resources, Big Picture
  • xHCI Internal Registers
    • PCI Configuration Registers
    • MMIO Registers
  • xHCI Memory Data Structures
    • Slot IDs, Doorbells, and Scheduling
    • Command Ring
    • Event Rings
    • Device Context Data Structure
    • Transfer Rings
  • xHCI Interrupts
    • Interrupters and Event Rings
    • MSI-X Configuration
    • Interrupt Moderation
  • xHCI Reset & Initialization
    • Host Controller Reset Types
    • Host Controller Initialization
  • Device Attachment & Initialization
    • Root Hub Port Status Change
    • Enable Slot & Address Device Commands
    • Device Context Setup
    • Configuration Selection

Part 3. Optional Additional Topics (Not covered in standard 4-day class. Contact MindShare)

  • USB 2.0 Review
    • USB 2.0 Topology
    • Host Controller Functions
    • How Transactions Are Generated
    • USB Transfer Types and Scheduling
    • Hub Operation
    • USB Communications Model
    • USB Configuration
  • ESS Signaling
    • Gen 1
    • Gen 2
  • ESS Link Testing
    • Compliance Testing
    • Receiver Loopback Testing
    • Gen 2 Differences

Recommended Prerequisites:

Background in USB 2.0 protocol is necessary

Training Materials:

Students will be provided with:

1.     An electronic (PDF) version of the presentation used in class

2.     MindShare’s USB 3.0 Technology eBook by Don Anderson and Jay Trodden 

3.     Optional: MindShare Arbor Software test/debug tool


USB 3.0 Technology