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Let MindShare Bring "PCI Express" to Life for You
MindShare's PCI Express System Architecture course starts with a high-level view of the design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.
This course describes additional features added to the architecture when moving from PCIe specification revision 1.1 to 2.0 to 2.1 to 3.0 . PCIe 3.0 (Gen 3) doubles the bandwidth available in revision 2.0 (Gen 2) by increasing the transfer rate and dropping 8b/10b encoding. But a number of protocol changes were also implemented in the change from revision 2.0 to 2.1, and those are described, too. The Gen 3 changes are physical layer updates to support the higher speed and some new steps that were needed for link training to get that speed working reliably, but the upper layers are left unchanged.
MindShare Courses On PCI Express 3.0, 2.x and 1.x:
All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.
Comprehensive PCI Express 3.0 Course Info
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You Will Learn:
- How PCIe is backward-compatible with PCI and PCI-X
- The definition and responsibilities of each of the layers in the interface
- How the hardware-based automatic error detection and correction mechanism works
- The various additional levels of error detection and reporting
- The details of the packet-based protocol used by PCIe
- The address space and packet-routing methods used
- How the various power management techniques work
- The details of the configuration registers that provide control and status visibility to software
- What are the ECNs related to PCI Express 2.1 specification
- What changes are needed to run the link at 8.0GT/s (rev 3.0 speeds)
- How to effectively use the Arbor tool for debug and verification of PCIe devices
Course Length: 5 days
Who Should Attend?
This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers.
Course Outline:
- PCI Architecture Background Foundation
- PCI Legacy Configuration Transaction Generation
- Config space exploration with the Arbor tool
- PCI Express Features and Architecture Overview
- Layered Architecture
- TLP, DLLP and Ordered Set Packet Format Overview
- Protocol Overview
- PCI Express Memory-Mapped Configuration Transaction Generation
- Packet Format Details
- Address Space and Transaction Routing
- Switch Routing Mechanism
- Address mapping labs with the Arbor tool
- Quality of Service and Arbitration
- TC/VC Mapping and VC/Port Arbitration
- QoS investigation with the Arbor tool
- Flow Control
- Flow Control Initialization
- Runtime Flow Control Update Mechanism
- Transaction Ordering
- ID-Based ordering (2.1)
- Simplified ordering table (2.1)
- ACK/NAK Protocol
- Error Recovery Mechanism
- Examples of Variety of Error Scenarios
- Nullified Packets and Store-and Forward vs. Cut-Through Mode
- Physical Layer Logic
- Byte Striping/Unstriping
- Scrambling/Unscambling
- 8b/10b Encoding/Decoding
- Serializing/Deserializing
- Error Detection and Handling
- Correctable, Non-Fatal and Fatal Errors
- Error investigation labs with the Arbor tool
- System Resets
- Fundamental Reset, Inband Reset, Function Level Reset
- Link Initialization & Link Training
- Detect, Polling, Configuration, L0 states
- Power Management States: L0, L0s, L1, L1 Active, L2, L3 Power States
- Physical Layer Electrical
- Electrical Changes for PCI Express 2.0
- Power Management
- Software controlled Power Management
- Active Hardware-based Power Management
- Latency Tolerance Reporting (2.1)
- Power management investigation with the Arbor tool
- Interrupt Support
- Legacy Interrupt Handling
- MSI Interrupt
- MSI-X Interrupt
- Interrupt investigation with the Arbor tool
- Dynamic Link Width and Speed Changes between 2.5 and 5.0 GT/s
- Hot Plug and Power Budgeting
- Dynamic Power Allocation (2.1)
- Add-in Cards and Connectors
- Introduction to Configuration
- PCI-compatible Configuration
- PCIe-specific Configuration and Registers
- PCI Express Capability Registers
- Detailed coverage with the Arbor tool
- Changes for PCIe 3.0
- Backward compatibility
- Higher speed
- Challenges for high speed designs
- Optimized buffer flush/fill
- Select ECN changes such as:
- Internal error reporting
- Multi-casting
- Atomic Operations
- Resizable BARs
- Alternative Routing-ID Interpretation
- Extended Tag enable
- TLP Processing Hints
Recommended Prerequisites:
A basic understanding of digital bus architectures such as PCI is highly recommended.
Training Materials:
1) MindShare will supply a copy of the "PCI Express Technology" eBook (covers PCIe 3.0)
MindShare’s PCI Express Technology textbook (PCIe 3.0)
Authors: Mike Jackson and Ravi Budruk
Publisher: MindShare Press
Available through the MindShare Store and major bookstore outlets. 2) Downloadable PDF version of the presentation slides
3) MindShare Arbor software tool, used for student labs in the class
4) Optional Comprehensive PCI Express 2.0 eLearning course (discounted pricing applies)
5) Optional PCI Express 2.1 and 3.0 Update eLearning course (discounted pricing applies)
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