ERRATA
PCI System Architecture, 3rd Edition

Errata/Clarifications for First Printing

• On page 23, the wrong picture is shown. Should show a bus buffer between the processor's local bus and the VESA VL Type B local bus and three VL devices on the VL bus.
• On page 31, row 5, 2nd column says "524Mbytes" should say "528Mbytes".
• On page 102, item 20, writeup was wrong. Should have read "A newly-latched DRC cannot pass a previously-latched DWC. The write request (associated with the DWC) was received before the read request (associated with the DRC), so the write must complete on the initiating bus before the read is permitted to complete (to ensure that the transactions complete in program order)." Note that the final rev 2.1 spec completely rewrote this entire section. These changes are reflected in the 3rd and greater printings of the PCI System Architecture book.
• On page 122, the following clarification of the multiple data phase special cycle transaction is substituted: "It is permissible for an initiator to deliver multiple packets of message information during the special cycle. No messages are currently defined that provide this capability, however. The target(s) latch the first message packet on the rising-edge of the clock when IRDY# is first sampled asserted. FRAME# would be kept asserted when IRDY# is asserted, indicating that there is at least one more data phase. The message type encoded on AD[15:0] may imply the number of additional message packets to be delivered or the data field encoded on AD[31:16] may state the number of packets. The second data phase starts during the clock cell immediately following the first assertion of IRDY#. Although the specification doesn't clearly state so, the author interprets the specification as indirectly stating that the initiator can deassert IRDY# during the second (and any subsequent) data phase until it has placed the next message packet on the AD bus. Each additional data phase completes when IRDY# is sampled asserted. During the final data phase, the initiator deasserts FRAME# when it asserts IRDY#, indicating that this the last data phase. When the final data transfer completes, the initiator must keep IRDY# asserted for at least four additional clocks before performing a master abort to return the bus to the idle state. This time period is required to give the target(s) sufficient time to "process" the message. The specification does not explain what form this "processing" might take (because it would be subsystem specific)."
• On page 150, 2nd row should say "Reserved." Third row should say "Cacheline wrap mode. Newly-defined in revision 2.1".
• Pages 178-179: descriptions of Disconnect C and Retry are incorrectly treated the same. The third printing of the book greatly expands this discussion to clearly define the differences between the two.
• On page 195, FRAME# should be shown transitioning to the deasserted state during clock 4.
• On page 253, 3rd bullet under 1st heading, "IO transactions do require" should read "IO transactions do not require".
• On page 259, remove stray "bubble" and arrow on ACK64# signal.
• On page 460, added the following text to indicate values returned by PCI BIOS Present function call: EDX contains the ASCII character string " PCI", with DL = "P", DH = "C", the byte above DL = "I", and the upper byte of EDX set to the ASCII space character. AH = 00h. BH = BIOS major version in BCD. BL = BIOS minor version in BCD. CL = the number of the last PCI bus in the system. Carry bit is cleared if BIOS present, set if it's not. The programmer is only assured that the PCI BIOS is present if EDX, AL and the carry flag contains the indicated information. The contents of AL indicates: whether host/PCI bridge supports configuration mechanism number one (bit 0 = 1) or two (bit 1 = 1); whether host/PCI bridge supports special cycle generation using configuration mechanism number one (bit 4 = 1) or two (bit 5 = 1).

Errata/Clarifications for Second Printing

We did not produce any errata for this version.

Errata/Clarifications for Third (and subsequent) Printings

This list last updated on 7/31/96.

The changes made between the second and third printings were substantial and are too extensive to include here. The PCI SIG released the final version of the 2.1 spec in June and the book was updated to reflect it. The following errors have been noted and will be corrected in a later version:

• On page 28, 2nd line under the heading "Longevity" should read "around the 386 and 486".
• On page 46, under heading "Old Method...", 2nd line should read "from a logic high to a logic low." 4th line should read "high to a low at the point..."
• On page 100, remove "The" at end of 1st line.
• On page 124, 3rd line from bottom, 1st word should be "addressed".
• On page 157, 4th table row, 2nd column, "IRDY# and TRDY#..." should read "IRDY# or TRDY#..."
• On page 178, the figure caption should read "Disconnect C Issued without IRDY# Asserted".
• On page 178, paragraph at bottom, 2nd line, "(including the first)" should read "(except the first which must adhere to the 16 clock rule)".
• On page 182, the figure caption should read "Retry Received without IRDY# Asserted".
• On page 290, last line of 1st paragraph, "electrical" is spelled wrong.
• On page 294, 3rd bulleted item at top, should read "...must be exactly 2.5 inches and...".
• On page 297, under heading "This Chapter", end of line 3 should read "PCI device".
• On page 338, last row, "classed codes" should read "class codes".
• On page 376, Table 18-6, "NA" row, "token ring" and "Baseband" are mis-spelled.
• On page 382, 3rd bullet at bottom, should read "Subordinate Bus. Highest numbered PCI bus that exists behind the bridge (on its secondary side).".
• On page 464, 1st row of table, 2nd column, {"_32_."} should read {"_32_".}
• On page 497, under heading "Clock Signal Source and Routing" last sentence should read "...must adhere to the clock signal trace length...".
• On page 501, 2nd table row, right column, "...and is only capable of proper operation when installed on a 66MHz bus" should read "...and requires the throughput available on a 66MHz bus"