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x86 Instruction Set Architecture
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Technical Titles
FireWire System Architecture (2nd Edition)
HyperTransport 3.1 Interconnect Technology
HyperTransport System Architecture
InfiniBand Network Architecture
ISA System Architecture (3rd Edition)
PCI Express System Architecture
PCI Express Technology 3.0
PCI System Architecture (4th Edition)
PCI-X System Architecture
SAS Storage Architecture
SATA Storage Technology
The Unabridged Pentium 4
Universal Serial Bus System Architecture
USB 3.0 Technology
x86 Instruction Set Architecture

Historical Titles
Heaven's Favorite - Book One Ascent: The Rise of Chinggis Khan
Heaven's Favorite - Book Two Dominion: Dawn of the Mongol Empire




x86 Instruction Set Architecture

Author(s): Tom Shanley
Publisher: MindShare Press
Pages: 1567
Retail Price: $99.99

Book Price:
$89.99
eBook Price
$42.00
Book + eBook Price
$109.99


Wikipedia Definition: The Instruction Set Architecture, or ISA, is defined as that part of the processor architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external IO.

With the exception of some small deviations and differences in terminology, all Intel and AMD x86 processors share a common ISA. This book focuses on those shared attributes (it does not cover those areas where the two companies have chosen widely divergent solutions which, by definition fall outside of the ISA specification).

If you’re looking for a comprehensive book designed to bootstrap you up quickly on virtually all aspects of the x86 32/64-bit Instruction Set Architecture (ISA), we respectfully ask you to consider this book. Tom Shanley, President of MindShare, Inc., applied his 40 years of hardware and software experience with Intel processors (from the 4004 and 8008 through the Nehalem-based processors of today) to this ambitious undertaking. The material organization is derived from those used to train thousands of software and hardware designers at virtually all of the world’s leading high-tech companies.

Essential topics covered include:

  • Basic Terms and Concepts
  • Mode/SubMode Introduction
  • A (very) Brief History
  • State After Reset
  • Intro to the IA-32 Ecosystem
  • Instruction Set Expansion
  • 32-bit Machine Language Instruction Format
  • Real Mode (8086 Emulation)
  • Legacy x87 FP Support
  • Introduction to Multitasking
  • Multitasking-Related Issues
  • Summary of the Protection Mechanisms
  • Protected Mode Memory Addressing
  • Code, Calls and Privilege Checks
  • Data and Stack Segments
  • IA-32 Address Translation Mechanisms
  • Memory Type Configuration
  • Task Switching
  • Protected Mode Interrupts and Exceptions
  • Virtual 8086 Mode
  • The MMX Facilities
  • The SSE Facilities
  • IA-32e OS Environment
  • IA-32e Address Translation
  • Compatibility Mode
  • 64-bit Register Overview
  • 64-bit Operands and Addressing
  • 64-bit Machine Language Instruction Format
  • 64-bit Odds and Ends
  • Transitioning to Protected Mode
  • Transitioning to IA-32e Mode
  • Introduction to Virtualization Technology
  • System Management Mode (SMM)
  • Machine Check Architecture (MCA)
  • The Local and IO APICs

Processor design-specific subjects such as Power Management and design-specific MSRs are not covered in this book. Rather, they are covered in MindShare's Processor family-specific microarchitecture classes.

MindShare's System Architecture Series is a crisply written and comprehensive set of guides to the most important computer hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel.

About the Author

Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.