|
|
 |
PCI Express 2.1 and 3.0 Updates eLearning Course
Instructor(s): Mike Jackson
Number of Modules: 5
Subscription Length: 90 days
 |
Course Price
$195.00 |
|
PCI Express 2.1 and 3.0 Updates Course Info
What's Included?
 |
 |
PCIe 2.1 and 3.0 eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
You Will Learn:
- How PCIe 2.1 implements multicasting capabilities
- Motivation for and implementation of TLP processing hints
- The benefits of an Alternate Routing ID
- How Resizable BARs are configured
- About the new ordering rules defined in PCIe 2.1
- How atomic operations work in a PCI Express environment
- What changes are needed to run the link at 8.0GT/s (rev 3.0 speeds)
- What updates have been added to optimize power management
Who Should View?
This update course covering the changes with PCI Express 2.1 (and anticipated updates with 3.0) is perfect for anyone already familiar with the PCI Express but just need an overview of the updates to this technology.
If you do not already have a background in PCI Express, Please check out our other eLearning courses on PCI Express:
Course Outline:
- Internal Error Reporting
- Describes the new features associated with reporting internal errors
- Multicasting
- Describes the motivation for multicasting capabilities in PCI Express and defines the implementation as well as gives an example
- Atomic Operations
- Discusses the old locking behavior and the new native support for atomic operations
- Resizable BARs
- Discusses the motivation and implementation of these resizable BARs
- Dynamic Power Allocation
- Defines new registers associated with this feature
- ID-Based Ordering
- Talks about the optional new ordering rules with PCIe 2.1
- Latency Tolerance Reporting
- Provides the new registers, rules and gives examples of this new feature
- Alternative Routing-ID Interpretation
- Describes the motivation for supporting numerous virtual functions and the implications of doing so
- TLP Processing Hints
- Describes the motivation and implementation of including processing hints in TLPs
- Expected 3.0 Feature: Higher Speed
- Discusses the changes in protocol and packet transmission that will be required when moving to higher speeds (e.g. 8.0 GT/s)
- Optimized Buffer Flush/Fill
- Walks through the benefits of devices coordinating their packet transmissions (buffer flushes) and how it may be implemented in 3.0
 | Course Modules |
| Module | Length | | Part 1: Internal Error Reporting and Multicasting | 35 minutes | | Part 2: Atomic Operations, Resizable BARs, and Dynamic Power Allocation | 27 minutes | | Part 3: ID-Based Ordering, Latency Tolerance Reporting, Alternative Routing ID | 39 minutes | | Part 4: TLP Processing Hints and Simplified Ordering Table | 33 minutes | | Part 5: High-Speed and Optimized Buffer Flush/Fill | 53 minutes | | |
|
