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Comprehensive PCI Express 2.0 Architecture eLearning Course
Instructor(s): Mike Jackson
Number of Modules: 21
Subscription Length: 90 days
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Course Price
$895.00 |
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Comprehensive PCI Express 2.0 eLearning Course Info
What's Included?
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PCI Express 2.0 eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
PCI Express eBook
(yours to keep, does not expire) |
Benefits of eLearning:
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
You Will Learn:
- How PCIe is backward-compatible with PCI and PCI-X
- The definition and responsibilities of each of the layers in the interface
- How the hardware-based automatic error detection and correction mechanism works
- The various additional levels of error detection and reporting
- The details of the packet-based protocol used by PCIe
- The address space and packet-routing methods used
- How the various power management techniques work
- The details of the configuration registers that provide control and status visibility to software
MindShare's PCI Express System Architecture course starts with a high-level view of the design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.
Who Should View?
This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers.
Course Outline:
- Background Foundation
- PCI and PCI-X basics that carry forward to PCI Express
- PCI Express Overview
- High level overview of PCIe
- Transaction Characteristics
- TLPs (memory, IO, config and message packets), DLLPs, Ordered-Sets
- Address Space and Transaction Routing
- Memory, IO and Config space and address-based, ID-based and implicit routing
- Quality of Service and Arbitration
- Traffic classes, virtual channels, and arbitration schemes
- Flow Control
- Protocol of flow control including credit values and frequency of transmission
- Transaction Ordering
- Ordering rules
- ACK/NAK Protocol
- Coverage of ACK/NAK state-machine and example scenarios
- Physical Layer Logic
- Byte striping, scrambling, 8b/10b, SerDes, Elastic Buffer, SKP ordered-sets
- Error Detection and Handling
- Correctable, Non-Fatal, and Fatal errors and how they're reported and handled (PCI-compatible, baseline, and advanced error reporting)
- System Resets
- Hot, Warm, Cold and Function-Level resets
- Link Initialization & Link Training
- LTSSM(Detect, Polling, Configuration, Recovery), link and lane numbering, loopback, etc.
- Physical Layer Electrical
- Hig-speed signaling, ISI, de-emphasis, differential signals, equalization, eye diagrams
- Power Management
- Device power states (D0, D1, D2, D3), link power states (L0, L0x, L1, L2, L2/L3 Ready, L3), Dynamic Link Width and Bandwidth Changes
- Interrupt Support
- Interrupt messages, MSI, MSI-X
- Hot Plug and Power Budgeting
- Hardware elements, software elements, power budgeting
- Add-in Cards and Connectors
- PC form factors, Backplane, ExpressModule, ExpressCard, PCIe Cables, and more
- Introduction to Configuration
- Basics of config space registers and accessing config space
- PCI-compatible configuration
- Coverage of how PCI config space applies to PCIe
- PCIe-specific configuration
- Coverage of PCIe-specific config space (extended config space)
 | Course Modules |
| Module | Length | | Chapter 1: Background and Foundation | 79 minutes | | Chapter 2: PCIe Architecture Overview (Part 1 of 2) | 79 minutes | | Chapter 2 - PCIe Architecture Overview (Part 2 of 2) | 62 minutes | | Chapter 3: Transaction Characteristics | 65 minutes | | Chapter 4: Address Spaces and Transaction Routing | 26 minutes | | Chapter 5: Quality of Service (QoS) and Arbitration | 53 minutes | | Chapter 6: Flow Control | 30 minutes | | Chapter 7: Transaction Ordering | 15 minutes | | Chapter 8: Ack/Nak Protocol | 33 minutes | | Chapter 9: Physical Layer - Logical Section | 59 minutes | | Chapter 10: Error Detection and Handling | 43 minutes | | Chapter 11: System Resets | 12 minutes | | Chapter 12: Link Initialization and Training | 56 minutes | | Chapter 13: Physical Layer - Electrical | 44 minutes | | Chapter 14: Hot Plug and Power Budgeting | 34 minutes | | Chapter 15: Power Management | 67 minutes | | Chapter 16: Interrupt Support | 32 minutes | | Chapter 17: Add-In Cards and Connectors | 18 minutes | | Chapter 18: PCIe Configuration | 31 minutes | | Chapter 19: PCI-Compatible Configuration | 29 minutes | | Chapter 20: PCIe-Specific Configuration | 51 minutes | | |
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