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Modern DRAM (DDR2/DDR3) Comprehensive
Location Santa Clara, CA
Date 12/2/2010 - 12/3/2010
Duration 2-days
Instructor John Swindle
Sponsor JEDEC, Agilent Technologies
Price $1,195.00
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Modern DRAM Architecture Course Info
JEDEC Solid State Technology Association and MindShare have teamed up to offer exceptional technical education classes related to JEDEC standards including new information on the JEDEC DDR3 specification and its latest updates.
DRAMs used in computers have ranged from asynchronous DRAMs through today's DDR3 SDRAMs. MindShare’s DRAM Technology Architecture course describes the development of computer memory systems and covers in-depth today’s most advanced DRAM technology. The course ultimately focuses on ultra-dense, high-speed DDR2/DDR3 technology. Memory cell theory, operation and key chip architecture differences from SDRAM through DDR3 are covered. The DIMM organization and raw card definitions will be covered, as well as bus implementations. Initialization of a memory module, including an overview of the SMBus protocol and how to use the address strapping is discussed. System design challenges, ranging from signal routing to error handling, are covered. Using waveform examples, the commands and basic differences between SDRAM, DDR, DDR2 and DDR3 are taught. DRAM controller design principles are also discussed. JEDEC announced the release of JESD 79-3C, which defines the JEDEC DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. Learn how these enhancements for JEDEC DDR3 will enable improved system performance, including increased memory densities in server applications and reduction in costs for thermal management.
You Will Learn:
- How a DRAM cell is organized
- Organization of a variety of memory modules
- How to read DRAM transaction waveforms so that you can debug a memory channel
- Electrical characteristics of DDR2/DDR3 signals
- Elements of DRAM controller design
- How to design a DRAM memory channel on a system board
Course Length: 2 days
Times:
Start time each day: 8:30am
End time each day: 5:00pm
Breakfast is available at 8:00am
Lunch provided between noon - 1:00pm
Location:
Torrey Pines Conference Room, Building 4
Agilent Technologies, Inc.
5301 Stevens Creek Blvd
Santa Clara, CA 95051
Who Should Attend?
This course is hardware centric but does describe DRAM memory and DRAM controller initialization. It is suitable for hardware engineers, but software/firmware engineers will benefit. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers.
Course Outline:
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DRAM Introduction
- DRAM Chip Overview
- DRAM Module Overview
- SMBus protocol and SPD EEPROM
- SDRAM Overview
- DDR1 Overview
- DDR2 Details
- What has changed from DDR1
- SSTL_18 defined
- Burst mode of 4 and 8 only (4 N prefetch)
- ODT including timings
- OCD (not used)
- Posted CAS AKA additive latency
- And command definitions
- DDR3 Details
- Fly-By Routing Read Example
- Read Calibration
- Fly-By Routing Write Example
- Write Leveling
- On-Die Termination
- ZQ Calibration
- Reset
- Package Mirroring
- Mode Register Changes
- System Design Challenges
- Board layout topics
- System architecture topics
- DRAM Controller implementation
- Overview Other Memory Technologies
- Demo of Agilent Technologies' DRAM Test and Debug tools
Recommended Prerequisites:
A basic understanding of memory architecture.
Training Materials:
MindShare will supply both hard copy and electronic versions of the presentation slides.
Sponsors:
JEDEC: www.jedec.org
Agilent: www.agilent.com
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