HyperTransport 3.1 Interconnect Technology
Author(s): Brian Holden, Jay Trodden, Don Anderson
Publisher: MindShare Press
Retail Price: $79.99
"Product designers will find this book a uniquely valuable tutorial and reference on HyperTransport link and HTX slot connector technologies including the HyperTransport 3.1 and HTX3 specification revisions. With extensive new content authored by Brian Holden, the long-time technical chair of the HyperTransport Consortium, the book is a personal trainer that effortlessly walks the reader through HyperTransport's strong set of features and rich potential. This book is a must-have for anyone in the semiconductor and system industries who is either working with or exploring the potential of working with HyperTransport technology."
- Mario Cavalli General Manager, HyperTransport Technology Consortium
HyperTransportTM technology has revolutionized microprocessor core interconnect. It serves as the central interconnect technology for nearly all of AMDs microprocessors as well as for a rich ecosystem of other microprocessors, system controllers, graphics processors, network processors, and communications semiconductors. It is a high-speed, low latency, point-to-point, packetized link. The latest version, HyperTransport 3.1, enables data transfer at rates of up to 51.2 GigaBytes per second. It is scalable, error tolerant, and designed for ease of use. It is also compatible with PCIe, PCI-X, PCI, and AGP buses and includes comprehensive power management and x86 platform support. The HTX and HTX3 specifications define a PC architecture I/O slot that provides the lowest latency slot access to a microprocessor available.
MindShare's HyperTransport 3.1 Interconnect Technology provides a comprehensive guide to all of the releases of HyperTransport technology, from 1.03, through 2.0, to 3.1. This book includes over 250 drawings and over 100 tables.
- Physical signals
- Packet protocol
- Flow control
- I/O Ordering Rules
- Error detection and error handling
- System management messaging and protocols
- Power management messaging and protocols
- Packet routing algorithms including fairness
- Device configuration
- Electrical interface power and signaling
- Signal equalization and phase alignment
- Channel specification and modeling
- HyperTransport bridging and switching
- PCIe, PCI-X, PCI, AGP and x86 compatibility
Additional topics covered include:
- The HTX and HTX3 slots
- Server platform design
- A history of HyperTransport
- Terminology through a detailed glossary
MindShare's Technology Series is a crisply written and comprehensive set of guides to the most important computer hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel.
About the Authors
Brian Holden has been Chair of the HyperTransport Consortium Technical Working Group since 2002. He serves also as Consortium Vice President and was made a HyperTransport Fellow in 2006. He was a co-founder of StrataCom, has served in CEO, CTO & Director roles in the communications semiconductor and microprocessor industries, and holds 17 U.S. patents.
Jay Trodden is an electrical engineer with over 15 years experience in electronics hardware design. For the past 10 years he has been teaching and developing courses on processors and IO bus architectures for MindShare.
Don Anderson has over 30 years of experience in the technical electronics and computer industry. He has authored 14 books covering various aspects of computer hardware and system design. Topics include system architectures, parallel bus technologies, serial bus technologies, and processor architectures. Don has trained thousands of engineers in the US and around the world. Before joining MindShare, Don worked for Compaq, Schlumberger, Geosource and Hewlett Packard.
For More HyperTransport Info:
||Please visit the HyperTransport Consortium's website (www.hypertransport.org) for more information about HyperTransport and related products and events.