The Unabridged Pentium 4
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Technical Titles
FireWire System Architecture (2nd Edition)
HyperTransport 3.1 Interconnect Technology
HyperTransport System Architecture
InfiniBand Network Architecture
ISA System Architecture (3rd Edition)
PCI Express System Architecture
PCI Express Technology 3.0
PCI System Architecture (4th Edition)
PCI-X System Architecture
SAS Storage Architecture
SATA Storage Technology
The Unabridged Pentium 4
Universal Serial Bus System Architecture
USB 3.0 Technology
x86 Instruction Set Architecture

Historical Titles
Heaven's Favorite - Book One Ascent: The Rise of Chinggis Khan
Heaven's Favorite - Book Two Dominion: Dawn of the Mongol Empire

The Unabridged Pentium 4

Author(s): Tom Shanley
Publisher: Addison Wesley
Pages: 1741
Retail Price: $79.99

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“In this monumental new book, Tom Shanley pulls together 15 years of history of Intel's mainline microprocessors, the most popular and important computer architecture in history. Shanley has a keen eye for the salient facts, and an outstanding sense for how to organize and display the material for easy accessibility by the reader. If you want to know what does this bit control, what does that feature do, and how did those instructions evolve through several generations of x86, this is the reference book for you. This is the book Intel should have written, but now they don't have to.”

—Bob Colwell, former Chief Architect of Intel's IA32 microprocessors from 1992-2000

The Unabridged Pentium 4: IA32 Processor Genealogy book provides an in-depth description and comprehensive reference to the Intel IA32 processor family. This book takes the evolutionary approach in describing the growth of the IA32 processor hardware and software architecture starting with the 386 processor and covering through the Pentium 4 with the Prescott instruction set extensions, the Pentium M and the Pentium 4 Xeon processors.

Key Topics:

  • Single Task/Multitasking OS Background
  • 32-bit Register Set
  • Real Mode
  • Protected Mode
  • Instruction Set
  • Virtual 8086 Mode
  • Demand Mode Paging
  • Interrupts and Exceptions
  • APIC Subsystem
  • Evolution of the IA32 Processors
  • Overview of the P6 Core
  • The P6 FSB operation
  • Processor Power Management
  • Pentium 4 Road Map
  • Pentium 4 System Overview
  • Pentium 4 Processor Overview
  • Pentium 4 PowerOn Configuration
  • Pentium 4 Processor Startup
  • Pentium 4 Core Description
  • Hyper-Threading
  • The Pentium 4 Caches
  • Pentium 4 Handling of Loads and Stores
  • The Pentium 4 Prescott
  • Pentium 4 FSB Electrical Characteristics
  • Intro to the Pentium 4 FSB
  • Pentium 4 CPU Arbitration
  • Pentium 4 Priority Agent Arbitration
  • Pentium 4 Locked Transaction Series
  • Pentium 4 FSB Blocking
  • Pentium 4 FSB Request Phase
  • Pentium 4 FSB Snoop Phase
  • Pentium 4 FSB Response and Data Phases
  • Pentium 4 FSB Transaction Deferral
  • Pentium 4 FSB IO Transactions
  • Pentium 4 FSB Central Agent Transactions
  • Pentium 4 FSB Miscellaneous Signals
  • Pentium 4 Software Enhancements
  • Pentium 4 Xeon Features
  • System Management Mode (SMM)

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About the Authors

Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.