• ARM architecture (ARMv8.x-A and ARMv9.x-A-A)
• Support for execution of 32-bit ARMv7-A code
• 64-bit ISA (registers, instruction set, system instructions, etc)
• Floating point and Neon
• Calling conventions
• Memory model and paging
• Exception and Interrupt handling, and the exception levels
• Exception Level 2, intended for virtualization support
• TrustZone overview (Secure monitor at Exception Level 3 plus secure world)
• Power management
• Debug

Note, v8A includes compatibility support for v7-A code execution. This support is covered, but not details of the v7-A architecture.

• Introduction to ARM 64-bit Architecture
• ARM architecture profiles, what is v8-A and the other architecture profiles
• ARM architecture extensions to v8-A, the v8.1A, v8.2-A, etc and v9-A
• v8-A introduction and rational
• Support for v7 legacy code
  • AArch32 and AArch64 state
  • v7 instruction set changes
    • Deprecation
    • Additional features (some new 64-bit features have also been added as new features available to 32-bit execution)
• 64-bit platform architecture overview
  • Sample SoC
  • MP Core
  • Interconnect (ACE or CHI)
    • Coherency and the interconnect
  • Distributed interrupt controller
  • Role of firmware
  • Booting
• A64 ISA
• Integer registers
• Instruction set
  • Integer operations
  • Memory operations
  • Stack
  • System instructions
    • System control registers
    • Relationship to v7 support and co-processors
  • Calling conventions
  • Memory access (DRAM and device)
    • Ordering model
    • Barriers
      • dmb, dsb, isb
      • load-acquire and store-release
      • Domains
    • Semaphores
    • Cache management
  • Floating point, advanced SIMD, crypto
    • Registers and instructions
  • Exception levels
    • The 4 exception levels
    • Stack model, handler and thread
    • Vector table
    • Core implementation choices
    • Switching AArch32 and AArch64 state
  • Exception and interrupt handling
    • Control of delivery of exceptions and interrupts
    • Syndrome registers
    • Switching exception levels
    • Return from exception
  • Paging
    • Memory management with page tables
    • 4K, 16K and 64K granules
    • Page sizes
    • Features achieved with page tables, such as execute never
    • Address space trickery – fields in pointers that are not part of the address, such as tags and pointer authentication
    • TLB management
• EL2 Overview
  • Processor features intended for virtualization
  • Use of exception levels
  • Memory management
    • Second level page tables
    • Memory partitioning
    • I/O MMU (SMMU)
  • The use of EL2 for UEFI execution during boot
  • Addition of Secure EL2 to the architecture
• Caches
  • Hardware cache coherency
  • Software responsibilities
  • Cache control in software
• Security (TrustZone)
  • TrustZone functionality
  • Secure memory
  • Links to TrustZone in other architectures
  • 32-bit or 64-bit TrustZone
  • Implications on exception levels, and the addition of secure EL2
  • Switching bitness of TrustZone
  • Dynamic TrustZone, also called Realms, part of ARM’s Confidential Compute Architecture
• Other topics
  • Core power management, external power controller
    • Power modes (dormant, shutdown)
    • WFI, WFE, SEV
  • Debug (hardware and software based debug)
  • RAS – Reliability, Availability, Serviceability
  • Boot process