CXL - Compute Express Link



Let MindShare Bring "Compute Express Link (CXL) 2.0 Architecture" to Life for You

Compute Express Link (CXL) is a high-bandwidth, low-latency serial bus interconnect between host processors and devices such as accelerators, memory controllers/buffers, and I/O devices. CXL is based on PCI Express® (PCIe®) 5.0 physical layer running at 32 GT/s with x16, x8 and x4 link widths. Degraded modes run at 16 GT/s and 8 GT/s with x2 and x1 link widths.

CXL interconnect adds coherency and memory semantics, thus allowing for its application in heterogeneous processing systems with a variety of host processors, memory subsystems and peripheral devices interconnected. CXL has applications in standard computer systems, Artificial Intelligence, Machine Learning, communication systems, and High Performance Computing. Emerging applications require a diverse mix of CPUs, GPUs, FPGAs, peripherals such as smart NICs, and other accelerators interconnected via an open industry standard protocol with the necessary features which CXL provides. CXL provides a rich set of three protocols that include 1) based on PCIe, 2) CXL.cache and 3) CXL.mem semantics. CXL uses the PCIe stack offering full interoperability with PCIe.

MindShare’s comprehensive CXL 2.0 Architecture course provides a solid foundation of platform architectures and use cases of the three CXL protocols with Type 1, Type 2 and Type 3 devices. The course then details the role of the Transaction Layer, Link Layer, ARB/MUX and Flex Bus Logical and Electrical Physical Layer of a CXL port design. We explain enumeration and configuration process during system bring-up with details of configuration registers. Other topics include: switch architecture, reset, manageability, RAS features, power management, performance considerations and compliance testing.

MindShare Courses On CXL Architecture:

Course Name

Virtual Classroom

CXL 2.0 Architecture 
4 or 5 days

4 or 5 days

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CXL Fundamentals 
1 day

1 day

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All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.

Compute Express Link (CXL) 2.0 Architecture Course Info

You Will Learn:

  • CXL system architectures with Type 1, Type 2 and Type 3 devices
  • CXL transaction protocol for and CXL.cache/mem
  • CXL port design constituting Transaction, Link, ARB/MUX and Flex Bus Physical Layers
  • CXL switch architecture (optional)
  • Enumeration and initialization issues with configuration register definitions
  • Power management
  • Reliability, Availability, Serviceability (RAS) and error handling features
  • Considerations to improve protocol performance

Course Length: 4 Days (5 Days with CXL Switch Architecture coverage)

Who Should Attend?

This course is hardware-oriented, but is suitable for both hardware design and software engineers given the course covers CXL initialization topics. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of CXL architecture. The course is also suitable for chip-level and board-level validation engineers.

Course Outline:

  • CXL Features and Architecture Overview
    • Limitations of interconnects that do not support coherency and memory semantics
    • CXL and Flex Bus Link features
    •, CXL.cache, CXL.mem overview
    • Type 1 (devices with cache), Type 2 (devices with memory) and Type 3 (memory expander with no compute engine) devices
    • Layered architecture overview
    • Transaction flows for PCIe, Type 1, 2 and Type 3 devices
    • Cache coherency and MESI protocol tutorial
  • CXL Transaction Layer
    • CXL.mem protocol
    • CXL.cache protocol
    • protocol
    • Ordering rules
  • CXL Link Layer
    • Link Layer
    • CXL.cache and CXL.mem common Link Layer
    • and CXL.cache/mem Flit packet format
    • Link Layer initialization
    • Flow control
    • CXL.cache/CXL.mem retry mechanism
    • CXL.cache Viral feature
  • CXL ARB/MUX Layer
    • Arbitration and Data Multiplexing/Demultiplexing feature
    • Virtual Link State Machine (vLSM) states
    • ARB/MUX Link Management packets and Bypass feature
  • Flex Bus Physical Layer
    • Protocol ID
    • NULL Flits
    • Byte Striping
    • Latency optimized mode (Sync Header Bypass mode)
    • Link training
  • Resets
    • Cold reset
    • Warm reset
    • Function Level reset (FLR)
    • CXL Reset
  • Power Management
    • Runtime control power management
    • Physical Layer power management
    • power management
    • CXL.cache + CXL.mem power management
  • RAS and Error Handling
    • RAS features
    • Error handling
    • Viral handling
    • Error injection
  • Enumeration and Manageability
    • Memory interleaving
  • Control and Status Registers
    • Differences between CXL 1.1 and 2.0 devices' register organization
    • DVSEC configuration registers including RCRB memory mapped registers
    • MEMBAR0/Component registers
  • Performance Considerations

Optional Topic (extra 1-day)

  • CXL Switch Architecture
    • Architecture overview with configuration options
    • and CXL.cache/mem transaction decoding and forwarding
    • Switch power management
    • Switch RAS (error handling)
    • Fabric Manager API to switch and Event Records

Recommended Prerequisites:

Good working knowledge of PCI Express a must. Computer architecture fundamentals. Knowledge of Intel, AMD or Arm processor architectures.

Training Materials:

  1. Downloadable PDF version of the presentation slides
  2. Optional CXL 2.0 Architecture eLearning courses


? US Pacific Time, 9am-5pm: 9/26/2023
? US Pacific Time, 9am-5pm: 9/26/2023