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Modern DRAM (DDR4 / DDR3 / LPDDR3 / LPDDR2) eLearning Course
Instructor(s): John Swindle
Number of Modules: 34
Subscription Length: 90 days
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Course Price
$695.00 |
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Modern DRAM (DDR4 / DDR3 / LPDDR3 / LPDDR2) eLearning Course Info
What's Included?
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DRAM eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
You Will Learn:
- How a DRAM cell is organized
- Organization of a variety of memory modules
- How to read DRAM transaction waveforms so that you can debug a memory channel
- Electrical characteristics of DDR2/DDR3/DDR4 signals
- Elements of DRAM controller design
- Differences between DDR1, DDR2, DDR3 and DDR4
- Characteristics and behavior of LPDDR2 and LPDDR3
Who Should View?
This course is hardware centric but does describe DRAM memory and DRAM controller initialization. It is targeted for hardware engineers, but would also benefit software/firmware engineers. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers.
Course Outline:
- Module 1: Introduction
- Intro to the course, outline, objectives
- Module 2: System Architecture
- DRAM in different platforms: x86 desktop, server, ARM SoC
- Module 3: DRAM Background
- DRAM history, types of RAM
- Module 4: DRAM Cell Architecture
- Bit line, word line, read/write/precharge basics, open cell array, folded cell array, sense amplifier
- Module 5a: DRAM Device Architecture
- DRAM array evolution, rows, columns, banks
- Module 5b: DRAM Device Architecture
- SDR, DDR1, DDR2, DDR3, DDR4, LPDDR1, LPDDR2, LPDDR3, core speed vs. IO speed
- Module 6: Fabrication and Packaging
- Redundancy, BGA packages, FBGA, Package-on-Package (PoP), 3D stacking
- Module 7: DRAM Feature Summary
- Covers main features of DDR1-DDR4 and LPDDR1-LPDDR4 as well as Wide IO, focuses on feature changes from DDR3 to DDR4, discusses related JEDEC standards and specifications
- Module 8: DRAM Controller Basics and Addressing
- Required controller blocks (address and control mux, refresh timer, PLL, timing generator, etc.), addresses and address translation
- Module 9: DRAM Modules
- Ranks, Dual Inline Memory Module (DIMM), Unbuffered Modules (UDIMM), Registered Modules (RDIMM), Load-Reduced Modules (LRDIMM)
- Module 10: DRAM Pin Descriptions
- Clock pins, control pins, command pins, address pins, data group pins, error status pins, power pins, reference pins, SPD pins, Reserved/Unused pins, DDR2 DIMM pins, DDR3 pins, DDR4 pins, LPDDR2/3 pins
- Module 11a: Commands and Waveforms
- DDR3 bank states, DDR4 bank states, DDR3/4 asynchronous reset
- Module 11b: Commands and Waveforms
- DDR3 commands, DDR4 commands, LPDDR2-S and LPDDR3 bank states, LPDDR2/3 commands
- Module 11c: Commands and Waveforms
- Initialization commands, mode register set command, activate command, speed bin numbers, activate waveform for DDR3/4 and LPDDR2/3, read command, burst orientation, burst type and length, burst order, banks and toggle-mode addressing
- Module 11d: Commands and Waveforms
- DDR3 and DDR4 read burst diagrams, additive latency, LPDDR2/3 read command
- Module 11e: Commands and Waveforms
- Write command, precharge command, auto precharge, refresh, self refresh, power down, DDR3/4 address and command timing, DDR3/4 3T timing, DDR4 CS# to command address latency
- Module 12: Refresh
- Retention and refresh interval, type of refresh, per-bank refresh, temperature controlled refresh, fine granularity refresh, partial array self refresh, self refresh, low-power auto self refresh, fast self refresh exit and self refresh abort
- Module 13: Electrical Specifications
- Stub series-terminated logic (SSTL), high-speed unterminated logic (HSUL), pseudo open drain (POD), low voltage swing terminated logic (LVSTL), DDR3 IDD / IDDQ specs, DDR4 IDD / IDDQ / IPP specs, LPDDR2/3 IDD / IDDQ specs
- Module 14: Power Management
- Power down and self refresh, deep power down and MPSM (maximum power saving mode), clock throttling
- Module 15: Signal Integrity Issues
- DQS timing, impedance (temp dependent), closed data eye because of ISI, jitter and more
- Module 16: On-Die Termination
- DDR3 and DDR4 ODT circuitry, ODT modes (asynchronous ODT, synchronous ODT, dynamic ODT, ODT park), DDR4 ODT timing examples
- Module 17: Signal Routing
- DDR1 and DDR2 routing, DDR3 and DDR4 fly-by routing read example, DDR3 and DDR4 fly-by routing write example
- Module 18a: DDR Initialization
- SPD data, DDR3 mode registers
- Module 18b: DDR Initialization
- DDR4 mode registers, LPDDR2 mode registers
- Module 18c: DDR Initialization
- Step-by-step DDR3/4 initialization, step-by-step LPDDR2/3 initialization
- Module 19a: Calibration and Training
- ZQ calibration
- Module 19b: Calibration and Training
- Read calibration, write leveling, CA training
- Module 19c: Calibration and Training
- DDR4 Vref training, DDR4 gear down mode
- Module 20a: Errors and Error Handling
- ECC, Scrubbing
- Module 20b: Errors and Error Handling
- DIMM parity, DDR4 CA Parity, DDR4 DQ CRC, DDR4 ALERT# timing
- Module 21: Testing
- Functional testing, parametric (pin) testing, diagnostic testing, burn-in and stress testing, DDR4 connectivity test mode
- Module 22: Optional: SMBus Overview
- SMBus features and architecture, physical layer, data link layer, packets and Ack/Nack overview, network layer, example read and write, SMBus commands
- Module 23: Optional: On-DIMM Address Mirroring
- Motivation, DDR3 and DDR4 pins that may be mirrored
- Module 24: Optional: Alternative DRAM Solutions
- Fully-Buffered DIMM (FB-DIMM), GDDR, GDDR5 features and comparison, RL DRAM, XDR
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