Intel Processor and Platform Architecture


Let MindShare Bring "Intel® Processor (Ice Lake & Cascade Lake) and Platform Architecture" to Life for You

Each CPU and chipset generation brings new capabilities while maintaining backward compatibility with earlier platforms. New 9th and 10th generation CPU architectures offer significant improvements in instruction throughput, power conservation, integrated graphics, security, system-on-a-chip (SOC) packaging options, etc. This 5-day course introduces the x86 Instruction Set Architecture (ISA) and describes the hardware features of the latest Intel Core and Xeon CPUs supporting it. In addition, the course presents an overview of memory, platform controller hub (PCH) logic, and IO interfaces that may be employed when implementing common system types.

A full understanding of an Intel x86 hardware platform includes knowledge of CPU/PCH capabilities, BIOS/OS setup of programmable platform features, as well as the dynamic status of the system with regards to thermal and error events, etc. MindShare Arbor demonstrations integrated into this course present a decoded view of register setup, system and device status, as well as a coherent summary of platform information reported when the CPUID instruction is executed. Students may use Arbor software for real-time scans of local systems, read/modify specific registers, and even save Arbor scan results for later sharing and off-line review.

This course is updated as frequently as possible in an attempt to provide a “snapshot” of current Intel Core and Xeon x86 platform components and system implementations. Content is based on publicly available documents.

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All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.

Intel Processor and Platform Architecture Course Info

You Will Learn:

  • Intel x86 CPU and Chipset Evolution
  • Current Core and Xeon CPUs: Ice Lake, Cascade Lake, plus “Refresh” Variants
  • x86 Instruction Set Architecture (ISA) and CPU Operating Modes
  • Core and Xeon CPU Microarchitecture Differences
  • Caches
  • Platform Addressing
  • Main Memory DRAM
  • Ultra Path Interconnect (UPI)
  • CPU Integrated Graphics
  • CPU Integrated IO (IIO)
  • Interrupt Handling
  • Hardware Virtualization Support
  • Platform Controller Hub (PCH) Features
  • Power and Thermal Management
  • CPU Performance Monitoring

Course Length: 5 days (but customizable to 4 days)

Course Outline

  • Intel x86 Core and Xeon Platform Background
    • Intel 64 and IA-32 CPU lineage
      • 80386 to Ice Lake/Cascade Lake
      • Core and Xeon CPUs Expected Next
    • Ice Lake/Cascade Lake Platform Examples
      • Gaming Desktop
      •  2-in-1 Laptop
      • Xeon Scalable CPU Server
  • x86 Instruction Set Architecture (ISA)
    • CPU Core Fetch/Decode/Execute Role
    • x86 Instruction Basics
    • Instruction Set Overview
      • General Purpose Instructions
      • Floating Point and SIMD Instructions
      • Program Flow Instructions
      • Hardware-Related Instructions
    • x86 Register Set Overview
      • General Purpose Registers (GPRs)
      • X87/MMX Registers
      • XMM/YMM/ZMM Registers
      • Segmentation Registers
      • Control Registers
      • Debug Registers
      • Model-Specific Registers (MSRs)
    • x86 CPU Operating Modes
      • Real Mode
      • Protected Mode
      • Virtual-8086 Mode
      • System-Management Mode (SMM)
      • IA32e (Long) Mode
  • Platform Addressing
    • Introduction to x86 Address Spaces
      • Memory (DRAM and MMIO Space)
      • IO (Fixed and Relocatable Legacy Registers)
      • PCI (Peripheral Component Interconnect) Space
    • Platform Traffic Types
      • Programmed IO (PIO)
      • DMA (Direct Memory Access)
      • Peer-to-Peer
    • Memory Segmentation
    • Real Mode
      • Protected Mode
      • Memory Paging
    • Paging
      • Translation Lookaside Buffer (TLB) Role
      • x86 Paging Modes: Basic 4K Paging, PSE, PAE, IA32e Mode Paging
  • Core CPU Microarchitecture (10th Generation Ice Lake)
    • CPU Internal Architecture Overview
    • Processor Instruction Pipeline & Execution Units
    • Implications of HyperThreading
  • Architectural Differences: Cascade Lake Xeon Scalable CPU vs. Ice Lake Core CPU
    • Maximum Core/Thread Count = 28/56
    • Enhanced AVX Execution Unit Resources
    • 32KB L1 Code/Data Caches, 1MB L2 Unified Cache
    • Non-inclusive L3 Cache with 2D Mesh Interconnect
    • L3 Cache Slice Distributed Caching/Home Agent (CHA)
    • ECC DRAM and Support for Persistent Memory (Optane) PMDIMMs
  • Cache Topics
    • Cache Basics
      • Five Memory Map Region Types: UC, WC, WB, WT, WP
      • Cache Policy Management: MTRRs and Paging Structures
    • CPU Conduct in the Five Memory Regions
    • Cache Hardware Architecture
    • Cache/Memory QoS and Intel Resource Director Technology (RDT)
      • Cache Monitoring Technology (CMT)
      • Cache Allocation Technology (CAT)
      • Code and Data Priority (CDP)
      • Memory Bandwidth Monitoring (MBM)
    • Other Cache Topics
      • PAT Feature
      • Software Prefetch Instruction
      • Non-Temporal Data
      • Data Direct IO (DDIO)
  • Key Platform Interfaces
    • CPU and PCH Interface Overview
    • Main Memory DRAM
    • Intel Ultra Path Interconnect (UPI)
    • PCI Express (PCIe)
    • Universal Serial Bus (USB)
  • PCI Configuration Space
    • Basics of Discovery and Enumeration
    • Client and Server Machine PCI Topology Examples
    • PCI Headers, Compatible Configuration Space, Extended Configuration Space
    • Accessing PCI Configuration Space
    • Arbor Software View of PCI Configuration Space
  • Platform Interrupt Handling
    • IOAPIC
    • Local APICs
    • Message Signaled Interrupt (MSI/MSI-X) Basics
  • Platform Power Management
    • ACPI Overview
    • CPU Power Management Features
    • PCH Power Management
    • IMC and DRAM Power Management
  • Platform Thermal Management
    • CPU Thermal Management Overview
    • PCH Thermal Management
    • DRAM Thermal Management
  • System Management Mode (SMM)
  • Machine Check Architecture (MCA)
  • Other Topics (Coverage Depends on Interest Level and Time Available)
  • Virtualization Overview

Recommended Prerequisites:

A basic understanding of computer architecture is helpful

Supplied Materials:

1) Course presentation PDF

2) MindShare’s “x86 Instruction Set Architecture” eBook by Tom Shanley

3) Optional Add-On: MindShare Arbor Software learning/test/debug tool

4) Optional Add-On: Intel Processor and Platform eLearning course



x86 Instruction Set Architecture