MIPI I3C
Training
 

Training

 NEW COURSE AVAILABLE FOR BOOKING NOW!

Let MindShare Bring "MIPI I3C Architecture" to Life for You

MIPI I3C (Improved Inter Integrated Circuit) is a two-wire, medium speed, multi-drop control bus originally intended to connect sensors in mobile devices to a processor. The full I3C communications protocol is defined in the MIPI I3C Specification which requires MIPI Alliance membership for access. Another version of the specification, referred to as MIPI I3C Basic, is publicly available and now provides nearly all of the same technical information as the full version of the specification. The features of I3C not covered in MIPI I3C Basic Specification are briefly described but the reader is directed to the MIPI Alliance (and the full version of the specification) for details. Fortunately, as the two specifications have evolved, MIPI has migrated most of the advanced features into the I3C Basic Specification---attracting more developers and expanding the reach of MIPI I3C into a wider range of embedded and mainstream computer applications. 

Many current applications rely on I2C (Inter Integrated Circuit) and SPI (Serial Peripheral Interconnect) for connecting sensors and other low-medium speed devices to a processor. MIPI I3C addresses long-standing limitations of both of these protocols and provides a path towards consolidating legacy interfaces into a single connection type that leverages positive features of I2C/SPI while adding new capabilities that are important as more diverse device types are supported. At the same time, MIPI I3C is an enhanced version of I2C and backward compatibility is a requirement.

Another aspect of I3C that enables scalability is the MIPI I3C Host Controller Interface (HCI) Specification. This helps standardize host interactions with I3C devices and defines two operational modes: DMA and PIO. HCI DMA mode is important in larger systems that have the memory resources to support a host controller model similar to that used by USB 3.x, SATA AHCI, and NVMe to off-load the CPU from much of the burden of managing device transactions. On the other hand, a MIPI I3C host controller operating in PIO mode may be better suited to an embedded system where logic, memory, and power resources are more scarce and something like a small microcontroller is responsible for interacting with an I3C controller and its devices using a small set of IO registers.

MindShare Courses On MIPI I3C Architecture:

Course Name
Classroom

Virtual Classroom

eLearning
MIPI I3C Architecture 
3 days

3 days
Notify Me When Available 

All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.


MIPI I3C Architecture Course Info

You Will Learn:

  • Major features defined in the MIPI I3C Basic Specification
  • How MIPI I3C addresses some of the long-standing speed, power, and pin count limitations of alternative IC communication protocols, including I2C and SPI
  • Why I3C devices dynamically switch data line drivers between push-pull and open drain signaling
  • The motivations for MIPI I3C Hot-Join for extremely power sensitive devices
  • How I3C compliant devices report bus and internal characteristics to software
  • How an enhanced set of direct and broadcast Common Command Code (CCC) transactions help simplify initialization, changing bus modes, and with device control and status operations
  • The use of I3C in-band interrupts (IBI) to reduce pin count and enable devices to send critical status information as part of the IBI payload.
  • Key features of the MIPI I3C Host Controller Interface (HCI) Specification

 


Course Length: 3 Days

Who Should Attend?

This MindShare course is designed for hardware/software engineers and others needing detailed coverage of MIPI I3C protocol.

Course Outline:

  • Key Specifications
    • MIPI I3C Specification and the MIPI I3C Basic Specification
    • MIPI I3C Host Controller Interface (HCI) Specification
  • Background: SPI/I2C Features and Limitations
    • SPI advantages and disadvantages
    • I2C advantages and disadvantages
  • Overview of Key I3C Features:
    • Master/Slave terminology deprecated in favor of Controller/Target
    • I3C devices: primary/secondary controllers, simple/composite targets, bridge devices, legacy I2C
    • I3C bus topology examples
    • Two-wire half-duplex signal interface: SDA/SCL
    • Dynamic switching of I3C bus data signal (SDA) between open-drain and push-pull operation
    • Data transfer speed options: Single Data Rate (SDR) and multiple High Data Rates (HDRs)
    • Software accessible registers to report device speed and other capabilities
    • Support for I3C read/write plus expanded set of Common Command Code (CCC) transactions
    • Improved I3C bus error detection and recovery
    • In-band Interrupt (IBI) replaces external GPIO pin required for external I2C or SPI interrupt
    • Hot-Join capability enables devices to leave and return to an I3C network for power conservation
  • I3C Single Data Rate (SDR) Protocol Details
    • SDR is the default traffic type for I3C devices
    • Overview of Controller and Target Roles
    • Initial and final I3C bus conditions: free/available/idle
    • I3C bus Open-Drain pullup and high keeper resistors
    • Generic I3C Frame
    • Device address variations
    • I3C SDR private read/write transfer examples
    • I3C Common Command Codes (CCCs): required and optional
    • I3C SDR CCC transfer examples
  • I3C High Data Rate (HDR) Mode
    • HDR-DDR is optional for controllers/devices but included in I3C Basic Specification
    • HDR Frames start in SDR mode, transition to HDR, and return to SDR mode when complete
    • Basics of HDR-DDR Entry/Exit Transitions
    • I3C HDR-DDR read example
    • I3C HDR-DDR write example
    • I3C HDR-DDR CCC example
  • In-band interrupts (IBI)
    • Device IBI request requires arbitration
    • The arbitration sequence
    • Source of the IBI payload: device status registers
  • I3C Bus Error Detection and Handling
    • Single Data Rate (SDR) errors
    • High Data Rate (HDR) errors
  • Target Reset
    • Controller reset of one or more targets
    • Reset of I3C peripheral vs. entire device
    • Reset used to signal exit from deep sleep state
    • Controller’s target reset signaling sequence
    • Target response to reset event
  • Bus Initialization
    • Primary and Secondary Controller Roles
    • Motivation for Dynamic Address Assignment (DAA)
    • DAA sequence of events
  • Hot-Join
    • Why is it supported?
    • Impact on I3C bus initialization
    • Rules for hot-join request from Target
    • Controller response
  • Electrical and Timing Requirements
    • I3C operating voltage & capacitance ranges
    • Common I/O requirements for push-pull and open drain modes
    • I3C-specific timing requirements
    • Special requirements for legacy I2C devices on I3C
  • Timing Control (Timestamp)—Optional Support
    • Motivation
    • Synchronizing device and controller reference clocks
    • May be used to coordinate power management transitions
    • I3C Timing Control Modes (only Asynchronous Mode 0 support in I3C Basic)
  • MIPI I3C Host Controller Interface (HCI)
    • Motivations and goals for MIPI I3C HCI
    • Some HCI terminology
    • Controller Modes: DMA, PIO
    • Supported I2C/I3C devices and speeds: optional vs. required
    • HCI resources: registers and memory
    • DMA mode ring operations
    • HCI in-band interrupt (IBI) support
    • HCI Error Handling


Recommended Prerequisites:

Some background in serial bus protocols such as I2C and SPI is helpful.

Training Materials:

Downloadable PDF version of the presentation slides