NVMe
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Training

Let MindShare Bring "Hands-On NVM Express (NVMe) 1.3" to Life for You

MindShare's NVMe (Non-Volatile Memory Express) course begins with a review of PCI Express (PCIe) basics as a foundation for the study of NVMe. Next, a high-level view of the architecture provides the big-picture context. Finally, we drill down into some details for each part of the design, providing an introduction to the hardware and software protocols. The course includes featches added to the 1,2, 1.2.1 and 1.3 specifications. 

MindShare Courses On NVMe:

Course Name
Classroom

Virtual Classroom

eLearning
Hands-On NVMe 1.3 Architecture
2 day

2 day

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NVMe-oF Architecture 
2 day

2 day
 Notify Me When Available
Hands-On PCI Express 3.1
5 days

5 days

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All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.


Hands-On NVM Express (NVMe) 1.3 Architecture Course Info

You Will Learn:

  • An overview of PCIe configuration
  • Basics of the NVMe Host Controller Interface model
  • The steps for device initialization
  • How command queues are set up and managed
  • How host software learns that commands have been completed
  • Which command sets are defined, what the commands are, and an overview of how they work
  • The error reporting structures defined
  • The power management options
  • Updates made to 1.2, 1.2.1 and 1.3 specifications

Course Length: 2 Day (but customizable down to 1 day)

Course Outline:

  • Basics
    • PCIe Background 
    • NVMe Host-Controller Interface overview
    • HANDS-ON ARBOR LAB: discover register addresses
    • Queue Management
      • Doorbell register operation
      • Tracking completion Phase Tag status
  • Commands
    • NVMe Admin Commands
    • NVMe IO Commands
    • Command execution 
      • Creation and management of Queues
      • Managing the queue: Doorbell register operation
      • Priority and Arbitration of commands
      • Completing commands
      • Informing the Host of completions
      • Handling Metadata
      • Asynchronous Event Notification
    • HANDS-ON ARBOR LAB: read commands from a queue
    • NVMe IO Commands
      • Setting up a data buffer
      • Command arbitration
      • Buffer addressing modes (PRPs vs. SGLs)
      • Get Features / Set Features – full coverage of features
    • HANDS-ON ARBOR LAB: use of get/set features - discover queue allocation
  • Architecture
    • Error reporting, Error Reporting Structures
    • Firmware updates
    • Controller registers
    • Controller initialization
    • Power Management
    • Reservations
  • Summary of changes for spec version 1.2
    • Enhanced power management hint
    • Option to use no local memory
    • Option to use large local memory for SQs
    • Live firmware updates
    • Additional commands for setting up Namespaces (to use with Reservations)
  • Summary of changes for 1.2.1
    • Identify Controller data – new fields
    • Use of NVM Qualified Name (NQN)
    • Keep Alive command added to support NVMe-oF
    • Extensions for HostID, Reservation Report, Get Log Page
  • Summary of changes for 1.3
    • Motivation for changes
    • Boot partitions
    • Thermal management by host
    • Write streams
    • Deallocation
    • Virtualization support
    • Debug support – Telemetry
    • Self-test options
    • Sanitize command
  • Appendices
    • Other NVMe commands
    • PCIe Architecture Overview

Recommended Prerequisites:

Previous exposure to PCIe is needed, as is some general knowledge of PC architectures.

Supplied Materials:

  1. Downloadable PDF version of the presentation slides.
  2. PCI Express Technology eBook (or hardcopy on request) by Mike Jackson and Ravi Budruk.
  3. Optional: MindShare Arbor software tool, used for student labs in the class.
  4. Optional: Comprehensive NVMe 1.2a eLearning course

 

 




? Santa Clara, CA: 12/1/2017

PCI Express Technology 3.0