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5-day Class |
4-day Class
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PCI Architecture Background Foundation |
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PCI concepts important for understanding PCI Express |
X |
X |
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Physical Address Spaces |
X |
X |
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Traffic Types (System Memory, PIO and DMA) |
X |
X |
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Typical System Transactions (NVMe Example) |
X |
X |
PCI Express Features and Architecture Overview |
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Layered Architecture |
X |
X |
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ARM example topology |
X |
X |
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TLP, DLLP and Ordered Set Packet Format Overview |
X |
X |
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Protocol Overview |
X |
X |
Configuration Overview |
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Legacy and Enhanced Configuration Access Mechanism (ECAM) |
X |
X |
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Type 0 and Type 1 Headers, Capability and Extended Capability Structures |
X |
X |
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Bus Enumeration |
X |
X |
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HANDS-ON ARBOR LAB: Scan your system and determine topology |
X |
X |
Address Space and Transaction Routing |
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Clarification of Memory space |
X |
X |
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System memory vs MMIO |
X |
X |
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Prefetchable vs Non-prefetchable |
X |
X |
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IO space |
X |
X |
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Setting up the BARs as well as the Base and Limit registers |
X |
X |
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Switch Routing Mechanism |
X |
X |
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HANDS-ON ARBOR LAB: Debug problem with address mapping |
X |
X |
TLP Format Details |
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Normal TLP fields |
X |
X |
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TLP Prefixes |
X |
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Lightweight Notification and TPH / Steering Tags |
X |
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10-bit Tags |
X |
X |
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PCI-SIG Vendor-Defined Messages |
X |
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Quality of Service and Arbitration |
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TC/VC Mapping |
X |
overview |
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VC Arbitration |
X |
overview |
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Port Arbitration |
X |
overview |
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Multi-function Arbitration |
X |
overview |
Flow Control |
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Flow Control Protocol |
X |
overview |
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Scaled Flow Control |
X |
overview |
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Link Feature Exchange |
X |
overview |
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Flow Control Initialization |
X |
overview |
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Runtime Flow Control Update Mechanism |
X |
overview |
Transaction Ordering |
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Simplified Ordering Table |
X |
X |
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Relaxed and ID-Based Ordering |
X |
X |
DLLP Format Details |
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DLLPs |
X |
X |
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NOP & Data Link Feature DLLPs |
X |
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ACK / NAK Protocol |
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TLP Error Recovery Mechanism |
X |
X |
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Simplified Replay Timer |
X |
X |
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Examples of Numerous Error Scenarios |
X |
X |
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Nullified Packets and Cut-Through Mode Switches |
X |
X |
Physical Layer Logic (2.5GT/s and 5.0GT/s) |
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Block Diagram |
X |
X |
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Ordered Sets |
X |
X |
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Byte Striping/Unstriping |
X |
X |
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Scrambling/Unscambling |
X |
X |
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8b/10b Encoding/Decoding |
X |
X |
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Serializing/Deserializing |
X |
X |
Physical Layer Logic (8.0GT/s, 16.0GT/s and 32.0GT/s) |
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128b/130b Encoding/Decoding |
X |
X |
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Control SKPs |
X |
X |
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Ordered-Set Blocks and Data Blocks |
X |
X |
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Data Streams and Packet Framing |
X |
X |
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Data Parity Checking |
X |
X |
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16.0 & 32.0 GT/s Data Parity Checking |
X |
X |
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Precoding |
X |
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Physical Layer Electrical (all speeds) |
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Differential Tx / Rx |
X |
X |
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2.5GT/s and 5.0GT/s De-emphasis |
X |
X |
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8.0GT/s, 16.0GT/s and 32.0GT/s Equalization Concept |
X |
X |
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Rx Equalization |
X |
X |
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Electrical Conditions for different Link States |
X |
X |
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Spread Spectrum Clocking (SSC) |
X |
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Separate Refclk Independent SSC (SRIS) |
X |
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Link Initialization and Training (LTSSM) |
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Detect, Polling, Configuration, L0 States |
X |
X |
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Recovery: Link Speed Change |
X |
X |
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Recovery: Equalization Process |
X |
overview |
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16.0 GT/s Equalization and Config Structures |
X |
overview |
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Negotiation for skipping parts or all of Tx Equalization |
X |
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32.0 GT/s Equalization and Config Structures |
X |
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Recovery: Link Width Change |
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L0s, L1, L2, Hot Reset, Link Disable and Loopback States |
X |
overview |
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Modified TS1 / TS2s and Alternate Protocol Negotiation |
X |
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Interrupt Support |
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Legacy Interrupt Handling |
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MSI Interrupts |
X |
X |
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32-bit MSI Data |
X |
X |
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MSI-X Interrupts |
X |
X |
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HANDS-ON ARBOR LAB: Investigate source of MSI(-X) interrupt and delivery |
X |
X |
Error Detection and Handling |
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Correctable, Non-Fatal and Fatal Errors |
X |
X |
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Advisory Non-Fatal Errors |
X |
X |
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Error Subclass field for Correctable Error Messages |
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Advanced Error Reporting (AER) |
X |
X |
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HANDS-ON ARBOR LAB: Determine source and error reporting mechanism |
X |
X |
Power Management |
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Device Power States |
X |
X |
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Link Power States |
X |
X |
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L1 Substates |
X |
X |
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Link Activation |
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Active State Power Management (ASPM) - hardware controlled |
X |
X |
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Software Controlled Power Management |
X |
X |
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Power Management Events (PME, Beacon and #WAKE) |
X |
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Dynamic Power Allocation (DPA) |
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Optimized Buffer Flush Fill (OBFF) |
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Latency Tolerance Reporting (LTR) |
X |
X |
System Resets |
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Conventional Reset Mechanisms: Cold, Warm and Hot Reset |
X |
X |
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Function Level Reset (FLR) |
X |
X |
Features Introduced with PCIe 4.0 |
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Retimers |
overview |
overview |
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Lane Margining |
overview |
overview |
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Flattening Portal Bridge (FPB) |
overview |
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Hierarchy ID Reporting |
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Designated Vendor-Specific Extended Capability (DVSEC) |
overview |
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Enhanced Allocation |
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Emergency Power Reduction State |
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Features Introduced with PCIe 5.0 |
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System Firmware Intermediary Support |
overview |
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Other PCIe Features |
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Hot Plug |
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Power Budgeting |
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Multi-Casting |
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Protocol Multiplexing (PMUX) |
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Resizable BARs |
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Downstream Port Containment (DPC) and Enhanced DPC (eDPC) |
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Lightweight Notification (can be used for lightweight cache coherency) |
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Process Address Space ID (PASID) |
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Precision Time Measurement (PTM) |
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Device Readiness Status (DRS) and Function Readiness Status (FRS) |
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