PCI Express


Let MindShare Bring PCI Express to Life for You

MindShare's PCI Express System Architecture course starts with a high-level view of the technology to provide the big-picture context and then drills down into the details for each topic, providing a thorough understanding of the hardware and software protocols.

The course describes additional features added to the architecture when moving through the PCIe specification revisions from 1.1 all the way to the latest 6.0. There are a large number of features and optional behaviors described in the PCIe spec. MindShare can customize the course to cover the topics that are most important for your group. Use the course outline below as a guide to request topics you want covered or removed. The table below contains a list of suggested course customizations.

MindShare Courses On PCI Express 6.0, 5.0, 4.0, 3.x, 2.x and 1.x:

Course Name

Virtual Classroom

PCI Express 6.0 
5 days

5 days

PCIe 1.x-5.0

PCI Express 5.0 
5 days

5 days

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PCI Express 6.0 Update 
3 days

3 days

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PCI Express for Software Engineers 
3 day

3 day
Fundamentals of PCI Express
1 day

1 day

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PIPE 6.0 - PHY Interface for PCI Express and more
1 day

1 day

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IO Virtualization for Intel Platforms
3 days

3 days

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IO Virtualization for ARM Platforms
3 days

3 days
Notify Me When Available  

All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.

Hands-On PCI Express Course Info

You Will Learn:

  • PCI Express features and capabilities
  • The definition and responsibilities of each of the layers in the interface
  • The PCIe packet-based transaction protocol details
  • The error detection, reporting and possible correction mechanisms
  • The address space and packet-routing methods used
  • How the various power management techniques work
  • The details of the configuration registers that provide control and status visibility to software
  • Software enumeration process
  • The process of transmitter equalization necessary to operate at 8.0GT/s, 16.0GT/s and 32.0GT/s
  • The details of the LTSSM including the concepts important for each state
  • PAM4 signaling
  • Flit Mode behavior

For SRIOV and ATS related topics, which are now incorporated into the PCIe base spec, please request our 3-day IO Virtualization for Intel Platforms or IO Virtualization for ARM Platforms as these topics are NOT covered in this standard 5-day PCIe course. PIPE 6.0 spec related topics are also not covered but can be requested. We cover ECNs listed below upon request.

Who Should Attend?

This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Given the in-depth architecture and design details covered, the course is also suitable for chip-level and board-level validation engineers.

Course Length: 5 days (but can be customized to shorter duration)

Course Outline:

5-day Class 5-day Class 3-day Class 3-day Class
PCIe 6.0 PCIe 5.0 PCIe 6.0 Update PCIe Software
PCI Architecture Background Foundation        
  PCI concepts important for understanding PCI Express
pre-class eLearning
X   X
  Physical Address Spaces X   X
  Traffic Types (System Memory, PIO and DMA) X   X
  Typical System Transactions (NVMe Example) X   X
PCI Express Features and Architecture Overview        
  Layered Architecture
pre-class eLearning
X   X
  ARM example topology X   X
  TLP, DLLP and Ordered Set Packet Format Overview X   X
  Protocol Overview X   X
Configuration Overview        
  Legacy and Enhanced Configuration Access Mechanism (ECAM)
pre-class eLearning
X   X
  Type 0 and Type 1 Headers, Capability and Extended Capability Structures X   X
  Bus Enumeration X refresher X
  HANDS-ON ARBOR LAB: Scan your system and determine topology X    
Address Space and Transaction Routing        
  Clarification of Memory space
pre-class eLearning
X   X
  System memory vs MMIO X   X
  Prefetchable vs Non-prefetchable X   X
  IO space X   X
  Setting up the BARs as well as the Base and Limit registers X   X
  Switch Routing Mechanism X   X
  HANDS-ON ARBOR LAB: Debug problem with address mapping X    
TLP Format Details        
  Normal TLP fields X X refresher  
  TLP Prefixes X X    
  10-bit Tags X X    
  PCI-SIG Vendor-Defined Messages X X    
Quality of Service and Arbitration        
  TC/VC Mapping   overview    
  VC Arbitration   overview    
  Port Arbitration   overview    
  Multi-function Arbitration   overview    
Flow Control        
  Flow Control Protocol X X refresher  
  Scaled Flow Control X X    
  Link Feature Exchange X X    
  Flow Control Initialization X X    
  Runtime Flow Control Update Mechanism X X    
Transaction Ordering        
  Simplified Ordering Table overview X    
  Relaxed and ID-Based Ordering overview X    
DLLP Format Details        
  DLLPs X X    
  NOP & Data Link Feature DLLPs X X refresher  
ACK / NAK Protocol        
  TLP Error Recovery Mechanism X X refresher  
  Simplified Replay Timer X X    
  Examples of Numerous Error Scenarios X X    
  Nullified Packets and Cut-Through Mode Switches X X    
Physical Layer Logic (2.5GT/s and 5.0GT/s)        
  Block Diagram X X    
  Ordered Sets X X refresher  
  Byte Striping/Unstriping X X    
  Scrambling/Unscambling X X    
  8b/10b Encoding/Decoding X X    
  Serializing/Deserializing X X    
Physical Layer Logic (8.0GT/s, 16.0GT/s and 32.0GT/s)        
  128b/130b Encoding/Decoding X X    
  Control SKPs X X    
  Ordered-Set Blocks and Data Blocks X X    
  Data Streams and Packet Framing X X    
  Data Parity Checking   X    
  16.0 & 32.0 GT/s Data Parity Checking   X    
  Precoding X X    
Physical Layer Electrical (all speeds)        
  Differential Tx / Rx X X    
  2.5GT/s and 5.0GT/s De-emphasis X X    
  8.0GT/s, 16.0GT/s and 32.0GT/s Equalization Concept X X refresher  
  Rx Equalization overview X    
  Electrical Conditions for different Link States   X    
  Spread Spectrum Clocking (SSC) overview X    
  Separate Refclk Independent SSC (SRIS) overview X    
Link Initialization and Training (LTSSM)        
  Detect, Polling, Configuration, L0 States X X refresher overview
  Recovery: Link Speed Change X X   overview
  Recovery: Equalization Process X X   overview
  16.0 GT/s Equalization and Config Structures X X   overview
  Negotiation for skipping parts or all of Tx Equalization X X    
  32.0 GT/s Equalization and Config Structures X X   overview
  Recovery: Link Width Change        
  L0s, L1, L2, Hot Reset, Link Disable and Loopback States   X    
  Modified TS1 / TS2s and Alternate Protocol Negotiation   X    
Interrupt Support        
  Legacy Interrupt Handling       X
  MSI Interrupts   X   X
  32-bit MSI Data   X   X
  MSI-X Interrupts   X   X
  HANDS-ON ARBOR LAB: Investigate source of MSI(-X) interrupt and delivery   X    
Error Detection and Handling        
  Correctable, Non-Fatal and Fatal Errors X X   X
  Advisory Non-Fatal Errors X X   X
  Error Subclass field for Correctable Error Messages       X
  Advanced Error Reporting (AER) X X   X
  HANDS-ON ARBOR LAB: Determine source and error reporting mechanism   X    
Power Management        
  Device Power States   X   X
  Link Power States   X   X
  L1 Substates   X   X
  Active State Power Management (ASPM) - hardware controlled   X   X
  Software Controlled Power Management   X   X
  Power Management Events (PME, Beacon and #WAKE)   X   X
  Dynamic Power Allocation (DPA)        
  Optimized Buffer Flush Fill (OBFF)        
  Latency Tolerance Reporting (LTR)   X   X
System Resets        
  Conventional Reset Mechanisms: Cold, Warm and Hot Reset X X   X
  Function Level Reset (FLR) X X   X
1b/1b Physical Layer (PCIe 6.0)        
  PAM4 X   X  
  Precoding, Gray Coding and Forward Error Correction (FEC) X   X  
  LTSSM Updates (TS0s, Tx EQ changes, entering Flit Mode, etc.) X   X  
Flit Mode        
  Flit Format X   X  
  Error Correction and Flit Retry (Standard vs Selective) X   X  
  DLP Bytes in Flit and Flit Types X   X  
  Flow Control (Dedicated vs Shared) X   X  
  TLP Structure (Header Base, OHC, TLP Trailer, etc.) X   X  
  Segments X   X  
  L0p X   X  
Miscellaneous PCIe Features        
  Retimers (introduced in 4.0) overview overview    
  Lane Margining (introduced in 4.0)   overview    
  Flattening Portal Bridge (FPB) (introduced in 4.0)   overview    
  Hierarchy ID Reporting (introduced in 4.0)        
  Designated Vendor-Specific Extended Capability (DVSEC) (introduced in 4.0)        
  Enhanced Allocation (introduced in 4.0)        
  Emergency Power Reduction State (introduced in 4.0)        
  System Firmware Intermediary Support (introduced in 5.0)   overview    
  Hot Plug        
  Power Budgeting        
  Protocol Multiplexing (PMUX)        
  Resizable BARs        
  Downstream Port Containment (DPC) and Enhanced DPC (eDPC)        
  Lightweight Notification (can be used for lightweight cache coherency)        
  Process Address Space ID (PASID)        
  Precision Time Measurement (PTM)        
  Device Readiness Status (DRS) and Function Readiness Status (FRS)        

Recommended Prerequisites:

A basic understanding of digital bus architectures such as PCI is recommended.

Training Materials:

1) MindShare will supply a copy of the "PCI Express Technology" eBook (covers PCIe 3.0) or hardcopy book on request

MindShare’s PCI Express Technology textbook (PCIe 3.0)
Authors: Mike Jackson and Ravi Budruk
Publisher: MindShare Press
Available through the MindShare Store and major bookstore outlets.

2) Downloadable PDF version of the presentation slides

3) Fundamentals of PCI Express (needed for pre-work before class)

4) Add-on Comprehensive PCI Express 5.0 eLearning course (discounted pricing applies)

5) Add-on PCI Express 6.0 Update eLearning Coruse (when released; discounted pricing applies)

3) Add-on MindShare Arbor software tool, used for student labs in the class (discounted pricing applies)


PCI Express Technology 3.0