This PLX article explains the use of PCIe Switches and Bridges in IO bandwidth optimization.

This PLX article discusses the ramifications of max payload size on protocol performance.

This PLX article discusses the effects of packet latency on performance.

This PLX article discusses how advanced new features such as read pacing, enhanced port configuration flexibility, dynamic buffer memory allocation, and the deployment of PCIe Gen2 signaling are reducing I/O bottlenecks, providing dramatic improvements in system performance in server and storage controllers.

This article by Agilent Technologies, describes the use of Oscilloscopes, Protocol Analyzers and Exercisers to test Physical, Data Link and Transaction Layers of PCI Express devices.

This article by PLX Technology describes how to eliminate unnecessary design steps, boost system throughput, and get some "free bandwidth" by using simple dual-casting techniques.

This article from ClearSpeed Technology and Cadence describes the methodology, tools used and implementation guidelines employed in designing a PCI Express based SOC.