PCI Express


MindShare-Authored White Papers
Introduction to PCI Express
Overview of Changes to PCI Express 1.1
Overview of Changes to PCI Express 2.1 and 3.0
Introduction to the PIPE Spec
Elastic Buffer Implementations in PCI Express Devices
PCI Express Replay Buffer Sizing

Other Industry-Expert Authored White Papers
Optimizing IO Expansion in Workstations
This PLX article explains the use of PCIe Switches and Bridges in IO bandwidth optimization.
Choosing PCIe Packet Payload Size
This PLX article discusses the ramifications of max payload size on protocol performance.
PCIe Packet Latency Matters
This PLX article discusses the effects of packet latency on performance.
Next Generation PCI Express Switches Eliminate IO Bottlenecks
This PLX article discusses how advanced new features such as read pacing, enhanced port configuration flexibility, dynamic buffer memory allocation, and the deployment of PCIe Gen2 signaling are reducing I/O bottlenecks, providing dramatic improvements in system performance in server and storage controllers.
Testing and Validating PCI Express Designs
This article by Agilent Technologies, describes the use of Oscilloscopes, Protocol Analyzers and Exercisers to test Physical, Data Link and Transaction Layers of PCI Express devices.
Free Up Bandwidth in PCI Express Designs
This article by PLX Technology describes how to eliminate unnecessary design steps, boost system throughput, and get some "free bandwidth" by using simple dual-casting techniques.
PCI Express Compliance Using a Predictable, Metrics-Based Verification Closure Methodology
This article from ClearSpeed Technology and Cadence describes the methodology, tools used and implementation guidelines employed in designing a PCI Express based SOC.

Other Resources
PCI Special Interest Group (PCI-SIG) Website

? 9am-5pm US Pacific Time: 8/1/2022
? 9am-5pm US Pacific Time: 8/1/2022

PCI Express Technology 3.0