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eLearning
SATA 3.2 Technology eLearning Course

Instructor(s): Don Anderson
Number of Modules: 25
Subscription Length: 90 days

Course Price
$795.00

 

SATA 3.2 Technology eLearning Course Info

What's Included?

SATA eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)
SATA eBook
(yours to keep, does not expire)

Benefits of eLearning:

  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course

You Will Learn:

  • The new features associated with the SATA Express SSDs and M.2 mobile cards
  • How the three SATA Express drives are detected
  • The mating compatibility of the SATA Express plug and receptacles
  • The compatibility associated with the M.2 modules and sockets
  • The sequence of events associated with SATA initialization, including Out Of Band (OOB) signaling
  • Detailed operation of a SATA HBA and drive when executing legacy commands
  • Details regarding the implementation and operation of the Advanced Host Controller Interface (AHCI)
  • How to verify proper command protocol associated with each of the command categories
  • How to verify proper control protocol associated with writes to the Control register
  • How to validate proper FIS (Frame Information Structure) protocol given trace captures from a SATA protocol analyzer
  • The actions taken by each layer in the SATA interface
  • The details associated with the implementation of Port Multipliers The operation and performance advantages of Native Command Queuing (NCQ)

Who Should View?

This course is hardware centric but does describe DRAM memory and DRAM controller initialization. It is targeted for hardware engineers, but would also benefit software/firmware engineers. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers.

Course Outline:

  • Module 1a: Evolution of Parallel ATA
    - This Module and the next combine to provide essential background for those who need an update regarding the Parallel ATA implementation. This section includes the Origins of ATA, ATA standard and releases, parallel ATA block diagram, pinout and legacy programming interface.
  • Module 1b: Evolution of Parallel ATA
    - ATA register details: logical block address (LBA), sector count, feature, command, data, status, error, control and alternate status register, multiple ATA interfaces, device signatures, overlap feature, device identify command
  • Module 2: Motivation for SATA
    - Motivation and design goals, Serial ATA topology, Major improvements made to cables and connectors (No more bent pins), New SATA drive plug/host receptacle, interface performance, improved reliability, lower voltages, migration to servers, SATA backward software compatibility
  • Module 3: SATA Overview
    - This module introduces the primary elements of SATA. Including: serial interconnect, OOB sequence for device detection, link initialization, Half-Duplex bus, Frame Information Structures (FIS), Shadow register for backward compatibility, SATA protocol layers implemented in both directions, Interface Layers include: application layer, command layer, transport layer, link layer, and physical layer), primitives, SATA command protocol, native command queuing (NCQ)
  • Module 4: FIS Types and Formats
    - Reference information describing the Frame Information Structures (FISes), (Register FIS Host to Device, Register FIS Device to Host, PIO Setup FIS, DMA activate FIS, Data FIS, Set Device FIS, First Party DMA Read Command, First Party DMA Write Command, First Party DMA Receive Command, First Party DMA Send Command, First Party DMA Setup, BIST Activate
  • Module 5a: Transport & Link Protocol Details
    - This Module covers the Transmission of FISes. Legacy vs Native operation, FIS Transmission, Overview of Transport and Link Layers, transmit arbitration conflict, list of primitives, CRC generation, start of frame (SOF) / end of frame (EOF) primitives, primitive suppression, FIS scrambling, CONT primitive, 8b/10b encoding
  • Module 5b: Transport & Link Protocol Details
    - This Module covers the reception of FISes. FIS reception, 8b/10b decoding, decoding / disparity error check, un-scrambler, CRC check, primitive decoding, completion status and error reporting, FIS transmission example
  • Module 6: FIS Retry
    - Most FISes can be retried, DATA FISes and BIST Activate FISes cannot be retried, error detection and retry, Transient Errors, Error reporting mechanisms: R_ERR and Host Errors
  • Module 7: Data Flow Control
    - Flow Control buffers in Transport Layer, Transmit Buffer nearly Dry and HOLD primitives sent, Receiver side returns HLDA, Transmit Buffer nearly Full, HOLD/HLDA released, Receive Buffer nears overflow and HOLD primitives sent, Transmitter sends HLDA. Receive Buffer nearly empty, HOLD/HLDA released
  • Module 8: Physical Layer Functions
    - Frame processing, ALIGN primitive insertion, serialization, differential transmission, differential receiver, clock recovery, data extraction, ALIGN detect, clock domains and elasticity buffer, OOB Signal Detect
  • Module 9: Error Detection & Handling
    - Error reporting methodology, error reporting registers, ignore or track, retry, abort, freeze, SATA error checks, phy layer errors/actions, link layer errors/actions, transport layer errors/actions
  • Module 10: Device Control Protocols
    - Control register, nIEN (interrupt enable), SRST (software reset), HOB (high order byte)
  • Module 11a: Device Command Protocols
    - 13 Command types, Command Not Implemented, Non-Data commands, PIO commands, device protocol for PIO data-in and PIO data-out, HBA protocol for PIO in and PIO out
  • Module 11b: Device Command Protocols
    - DMA-In (DMA read) device and HBA protocol, DMA data-out (DMA write) device and HBA protocol, DMA Queued Commands, First Party DMA commands, packet command protocol, Device Reset, Execute Device Diagnostics
  • Module 12: Native Command Queuing (NCQ)
    - The performance problem, benefits of NCQ, system support requirements, SActive Register, Command Issue Register, Set Device Bits, new commands: read FPDMA queued, write FPDMA queued, NCQ non-data, send FPDMA queued, receive FPDMA queued, DMA Setup FIS, Auto-Activate, Non-Zero Offsets, General Purpose Logging Feature Set, Queued Error Log feature, Read Log Ext command
  • Module 13: Port Multipliers
    - Purpose, PM port numbers, PMP numbers via Software,15 ports, packet switching, FIS routing across PM, collisions and collision resolution, PM initialization, read PM command, write PM command, Event Counters, hot plug support
  • Module 14: Port Selectors
    - Fail-Over Capability, Port selector functions, port selector detection, active host port selection, protocol switching
  • Module 15: Enclosure Services
    - SAF-TE and SES, SEMB, SEP
  • Module 16: SATA Initialization (OOB & Speed Detect)
    - SATA reset sequence, OOB signaling, SATA speed negotiation, asynchronous signal recovery, software initialization
  • Module 17: Analog Front-End & Electrical Details
    - Bit Error Rate (BER), differential signaling, reflections, impedance mismatches, many usage models, Compliance Testing
  • Module 18: Link Power Management
    - Power management command, partial / slumber transitions, COMWAKE protocol, exit latencies, Host Initiated handshake sequence, Device Initiated handshake sequence, Automatic partial to slumber
  • Module 19: Hot Plug
    - Hot Plug Operation: Power Present/not Present, Hot plug requirements, detection, current limiting, hot plug connections, Hot Plug Applications (Asynchronous Hot Plug/Removal, UnPowered OS Aware, Powered OS Aware, Surprise Hot Plug/Removal)
  • Module 20: Built-in Self Test (BIST)
    - BIST active process, test variations, test patterns, far end analog loopback, far end retimed loopback (required), far end transmit only, near end analog loopback
  • Module 21: Cables / Connectors
    - Internal vs external, connector signals, cables and multilane SATA connectors, slimline connectors, micro SATA connector, internal LIF, mini-SATA (mSATA), Universal Storage Module (USM), eSATA cable
  • Module 22: SATA Express
    - Legacy SATA 600 MB/s, PCIe SSDs (2 GB/s) and SATA SSDs (1GB/s) x 2 ports, mating plugs and receptacles, SATA Express Interface Detect, M.2 connectors, sockets, card dimensions, Mobile Devices, M.2 SATA Drives - 1.5 Gb/s, 3.0 Gb/s, 6.0 Gb/s, M.2 PCIe Drives - 2.5 GT/s, 5.0 GT/s, 8GT/s



SATA Storage Technology