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NEW COURSE AVAILABLE FOR BOOKING NOW!
Let MindShare Bring "Ultra Accelerator Link (UALink) Architecture" to Life for You
The UALink specification outlines a set of protocols and interfaces designed to form systems using multiple System Nodes aimed at AI applications. Each System Node normally includes one or more Host CPUs and Accelerators connected by various interconnects such as CXL, PCIe, AMD Infinity Fabric, etc. These nodes typically allow coherent access across Host and Accelerator memory within the node. Each node operates under a single OS image. UALink supports low-latency communication between Accelerators across System Nodes, allowing direct read, write, and atomic transactions. This inter-node communication is restricted to Accelerator initiated traffic. UALink protocol does not permit Host CPU access to memory across different System Nodes.
The UALink specification defines the UALink interface between different physical devices connected by a Link. The specification not only includes the traditional description of a serial bus stack (Transaction, Data Link and Physical Layer), but also includes a description of a UALink Protocol Level Interface (UPLI) also referred to as the Protocol Layer. The UPLI facilitates the standardization of an interface between a component and the UALink stack whether the component be an Accelerator core or a Switch core.
The UALink physical interface is a high bandwidth 200GT/s per Lane, maximum 4 Lanes, point-to-point serial interface Link between Accelerators and Switches, promoting a switching ecosystem for Accelerators. The UALink allows for up to 1024 Accelerators or endpoints in a network to communicate using a 10-bit Identifier.
MindShare’s comprehensive UALink 1.0 Architecture course provides a solid foundation of platform architectures and use cases of the UALink protocol. The course details the role of each of the layers in the stack. These include the Protocol Layer, Transaction Layer, Data Link Layer and Ethernet PHY Layer. We explain UALink Address Translation Model, Remote Memory Access (RMA) and UALink IO Coherency Model, UPLI operating rules, RAS, manageability and UALink Switch architecture, including configuration.
MindShare Courses On UALink Architecture:
All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.
UALink Architecture Course Info
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You Will Learn:
- UALink spec terminology
- Function of each layer that makes up the UALink port stack
- UPLI interface definitions and operating rules along with interface signals
- Tx and Rx compression caches
- TL Flit and Half Flit formats as well as DL Flit format
- DL message format
- TL Flow Control and DL Replay support
- Physical Layer encode/decode and FEC plus transmit and receive functions
- UALink RAS support
- Reset, signaling and connection
- Manageability requirements
- UALink Switch architecture and routing schemes
Course Length: 3 Days
Who Should Attend?
This course is hardware-oriented but is suitable for both hardware design and software engineers. The course is ideal for RTL-, chip-, system- or system board-level design, verification and validation engineers who need a broad and in-depth understanding of UALink system architecture
Course Outline:
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3-Day Class
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1-Day Class
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Topics
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UALink 1.0
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UALink Fundamentals
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UALink Features and Architecture Overview
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Accelerator System Node and Multi-Node architecture
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X
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X
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UPLI and Stack Layers overview
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X
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X
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Address Translation Model
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X
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X
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RAS overview
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X
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X
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UALink Switch overview
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X
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X
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UPLI and Protocol Layer
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UPLI Interface and Interface Signals
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X
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Requests and Response paths
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X
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Time Division Multiplexing
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X
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UPLI Flow Control
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X
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UPLI Transactions
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X
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Ordering Rules for Read and Write Requests and Responses
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X
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Transaction Layer
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TL features
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X
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TL Flit and Half Flit formats, sequencing and packing
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X
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TL Write Flit Sequence Encoding
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X
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Tx and Rx Compression Caches
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X
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TL Flow Control and Backoff Modes
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X
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Data Link Layer
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DL features
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X
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DL Flit formats and packing
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X
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DL Messages
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X
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Transmitter Pacing
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X
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Link Level Replay
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X
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DL States and Errors
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X
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Physical Layer
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PL features
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X
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Reconciliation Sublayers
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X
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PCS/PMA modifications
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X
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PCS and FEC
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X
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Low Latency FEC Interleave
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X
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UPLI Reset, Signaling and Connection
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UPLI Reset and Signaling
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X
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UPLI Control
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X
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RAS and Error Handling
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RAS requirements and End-to-End Data Protection
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X
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RAS error types
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X
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RAS error handling
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X
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Manageability
For Accelerators and System Nodes
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X
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For Switches and Switch Platforms
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X
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For Pod Controllers and Virtual Pods
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X
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Manageability Workflows
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X
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UALink Switches
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Bifurcation support
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X
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Lossless Request and Response delivery
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X
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Non-blocking architecture
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X
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Forward progress guarantee
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X
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Ordering Rules and Virtual Channels
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X
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Routing Table structure
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X
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Configuration
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X
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Switch debug recommendations and Latency/Performance goals
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X
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Recommended Prerequisite:
Computer architecture fundamentals. Suggested knowledge of high-speed serial bus architectures such as PCIe
Training Materials:
- Downloadable PDF version of the presentation slides
- UALink eLearning course when available
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