ARM 32-bit Architecture (ARM v7) eLearning Course

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ARM 32-bit Architecture (ARM v7) eLearning Course

Instructor(s): Paul Devriendt
Number of Modules: 25
Subscription Length: 90 days

Course Price
$695.00



ARM 32-bit Architecture eLearning Course

What's Included?

ARM 32-bit eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)

Who Is This Course For?

The ARM 32-bit Architecture eLearning course focuses on software-related aspects of the ARMv7 Architecture, with a specific focus on Cortex-A and Cortex-R profiles, plus common subjects like software tools. This course is aimed at embedded software and systems developers who would like to acquire a broad knowledge of ARM technology with a bias toward application processors and real-time processors.

This was the only eLearning course endorsed by ARM for anyone wanting to take the ARM Accredited Engineer (AAE) certification exam when ARM was still offering their AAE certification program. That program has been discontinued by ARM, but the information in this course is still very relevant and extremely valuable for anyone working with ARM v7 architectures.

ARM Endorsement

“On the strength of MindShare’s position as an industry leader in technology training, particularly in the area of microprocessor architecture, we were happy to welcome them to the AAE program as an ARM Accreditation Training Partner (AATP). Their expertise in delivering engaging self-paced eLearning courses should make MindShare's ARM Accredited Engineer Certification eLearning course a very good way to efficiently and cost-effectively prepare for the ARM Accredited Engineer (AAE) exam”.
- Daniel Dearing, AAE Program Manager

Benefits of eLearning:

  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready

Course Outline:

  • Module 1: ARM Introduction
    - Discusses the contents of the course and provides an intro to ARM the company
  • Module 2: Sample SoCs and Multiple Processor Cores
    - Provides high-level descriptions of several common ARM-based SoCs and goes over the concepts of multiple cores and multi-processing (SMP vs. AMP)
  • Module 3: ARM Processor Architectures
    - Goes through the ARM architecture evolution (v5, v6, v7 and v8) as well as the architecture profiles (-A, -R and -M)
  • Module 4: Architecture Introduction
    - Provides a high-level overview of the instruction sets supported and introduces the concepts of privilege levels and exception levels
  • Module 5: Integer Registers
    - Discusses the integer registers of the ARM architecture, the purpose and behavior of register banking and the Program Status Register
  • Module 6a: Instructions - ARM
    - Provides info on the ARM assembler syntax, numerous data processing instructions including some on bit manipulation as well as saturation effects
  • Module 6b: Instructions - ARM
    - Goes through the branch, conditional branch and branch/link instructions as well as how condition codes on instructions behave
  • Module 7: Instructions - Thumb/2, Jazelle, VZP and Neon
    - Covers the differences between ARM and Thumb/Thumb2 instructions and then goes through several examples of conditional execution in Thumb (If/Then/Else); Jazelle, Vector Floating Point and Neon instructions are also discussed at a high level
  • Module 8a: Memory Accesses
    - Discusses alignment of memory accesses, endianness and numerous LDR/STR addressing examples including a discussion on pre- versus post-indexing; memory copy examples are also covered
  • Module 8b: Memory Accesses
    - Defines the supported memory types and then goes through access ordering, several memory barrier examples, a semaphore synchronization example as well as the behavior of self-modifying code; Shareability domains are also covered
  • Module 9: Privilege, Modes, State, TrustZone and more
    - Covers Privilege Levels, the basic processor modes, provides an overview of TrustZone, the implemented virtualization extensions, and the concept of coprocessors
  • Module 10: Exceptions and Interrupts
    - Goes over the behavior of exceptions and interrupts including some info on common interrupt controllers
  • Module 11: Memory Management and Protection
    - Discusses the memory management behavior typical in the -M profile as well as the memory protection scheme commonly used in the -R profile
  • Module 12: Paging
    - Provides a great introduction to managing and protecting memory using paging (typical in -A profile), includes a discussion of TLBs and their management
  • Module 13: v7 LPAE and Hardware Virtualization
    - Covers the implementation of large physical addresses in the v7 architecture as well as the affects of hardware virtualization on paging
  • Module 14: Debug and Analysis Support
    - Discusses the different levels of debug that can be used and how each works
  • Module 15: Caches
    - Goes over the basics of caching, including cache line states, coherency and cache policies; Then shows Cortex-A9 caches as an example
  • Module 16: The Different Processor Cores
    - Provides an overview of some of the older ARM processor families, including descriptions of their instruction pipelines
  • Module 17: Cortex-M0/1/3/4 and Cortex-R4/5
    - Discusses the feature set and instruction pipelines of the Cortex-M0, Cortex-M0+, Cortex-M3/-M4 as well as the Cortex-R4 and Cortex-R5
  • Module 18: Cortex-A8/9/5
    - Discusses the feature set and instruction pipelines of the Cortex-A8, Cortex-A9 and Cortex-A5
  • Module 19: Cortex-A15/7/12
    - Discusses the feature set and instruction pipelines of the Cortex-A15, Cortex-A7 and Cortex-A12
  • Module 20: AMBA - The Buses
    - Provides a brief discussion on AMBA 3, AMBA 4 as well as AXI and the coherency extensions added to this interconnect
  • Module 21: Power Management and Booting
    - Covers an intro to power management on ARM-based systems as well as a generic boot process
  • Module 22: Software Development
    - Provides an overview of the software development process which includes a discussion of the purposes of the compiler and linker as well as object files, libraries (static vs dynamic) and the ARM ABI (Application Binary Interface)
  • Module 23: Software Optimization
    - Discusses what to optimize as well as the order of effort applied for code optimization; Includes topics such as: pointer aliasing, loop termination, parameter passing, compiler options, inline examples, variable types, data layout and packing of structures, base pointer optimization and more. Also briefly touches on some profiling tools and what they are useful for.
Course Modules
ModuleLength
Module 1: ARM Introduction16 minutes
Module 2: Sample SoCs and Multiple Processor Cores30 minutes
Module 3: ARM Processor Architectures29 minutes
Module 4: Architecture Introduction32 minutes
Module 5: Integer Registers42 minutes
Module 6a: Instructions - ARM47 minutes
Module 6b: Instructions - ARM33 minutes
Module 7: Instructions - Thumb/2, Jazelle, VFP and Neon35 minutes
Module 8a: Memory Accesses29 minutes
Module 8b: Memory Accesses52 minutes
Module 9: Privilege, Modes, State, TrustZone and others21 minutes
Module 10: Exceptions and Interrupts61 minutes
Module 11: Memory Management and Protection20 minutes
Module 12: Paging37 minutes
Module 13: v7 LPAE and Hardware Virtualization16 minutes
Module 14: Debug and Analysis Support56 minutes
Module 15: Caches67 minutes
Module 16: The Different Processor Cores53 minutes
Module 17: Cortex-M0/1/3/4 and Cortex-R4/518 minutes
Module 18: Cortex-A8/9/534 minutes
Module 19: Cortex-A15/7/1219 minutes
Module 20: AMBA - The Buses9 minutes
Module 21: Power Management and Booting31 minutes
Module 22: Software Development41 minutes
Module 23: Software Optimization57 minutes