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ARM 64-bit Architecture (ARM v8-A) eLearning Course
Instructor(s): Paul Devriendt
Number of Modules: 22
Subscription Length: 90 days
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Course Price
$895.00 |
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ARM 64-bit Architecture (ARM v8-A) eLearning Course Info
What's Included?
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ARMv8-A eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
You Will Learn:
- ARM architecture (ARMv8-A)
- Support for execution of 32-bit ARMv7-A code
- 64-bit ISA (registers, instruction set, system instructions, etc)
- Floating point and Neon
- Calling conventions
- Memory and paging
- Exception and Interrupt handling, and the exception levels
- Virtualization (Exception Level 2)
- TrustZone overview (Exception Level 3)
- Power management
- Debug
Who Should View?
This course is aimed at software developers and system architects developing for systems powered by ARMv8-A processors such as Cortex-A53 and Cortex-A57 Processors. It is relevant for operating system development, device drivers, low-level coding and for application software.
Course Outline:
- Module 1: ARM Introduction
- ARM company history, ARM business models, ARM naming conventions, ARM architecture profiles, defining terms like Core, MP-Core, Processing Element (PE), etc.
- Module 2: ARMv8-A 64-bit Overview
- Introduces topics like: 64-bit virtual addressing, AArch64 vs AArch32, A64 ISA, LP64 and LLP64, instruction encodings, processor registers, exception levels
- Module 3: Integer (General Purpose) Registers
- 64-bit usage, Stack Pointer (SP), Program Counter (PC), Link Register (LR) and Exception Link Register (ELR), 32-bit arithmetic examples, 64-bit and 32-bit register relationship
- Module 4: Processing Element State (PState)
- PState Register, Flag/Status bits, Extension/Control bits, DAIF and interrupt control, stack select, MRS, MSR and System Registers, PState and SPSRs
- Module 5a: A64 Instructions
- v7-A instruction functionality changes, AArch32, v8-A Jazelle and Java Bytecodes, listing instruction categories with examples of each (arithmetic, logic, etc.), instruction encoding
- Module 5b: A64 Instructions
- PC relative addressing, bit manipulation, branch and subroutine call, branch prediction, conditional branches and condition codes
- Module 6: System Instructions and Calling Conventions
- System calls (SVC, HVC, SMC), debug instructions, system register access instructions, architectural "hint" instructions, ELF ABI usage, ELF Frame Pointer
- Module 7a: Memory Accesses
- Load/Store architecture, addressing modes, load/store indexing and auto incrementing, multi-register loads/stores, little endian vs big endian, data alignment, instruction alignment, unaligned (misaligned) accesses
- Module 7b: Memory Accesses
- Accessing devices with memory instructions, memory types and rules, domains (NSH: non-shareable, ISH: inner shareable, OSH: outer-shareable, SY: full system), memory coherency, weakly ordered, memory barrier instructions (DMB: data memory barrier, DSB: data synchronization barrier, ISB: instruction synchronization barrier), JIT / self-modifying code
- Module 7c: Memory Accesses
- Device memory attributes (gathering, reordering, early write acknowledgement hint), memory access restrictions, semaphore flow, semaphore instructions, load-acquire and store-release, non-temporal load/store
- Module 8: Floating Point, SIMD and Crypto Extensions
- SIMD and Advanced SIMD, floating-point types (half-precision, single-precision, double-precision), floating point registers, SIMD registers, SIMD enhancements over v7-A, status and control registers, conversions to/from floating point, crypto functionality, cryptographic AES, cryptographic SHA, cryptographic CRC32
- Module 9: Exception Levels
- EL0 (application), EL1 (OS), EL2 (hypervisor), EL3 (secure monitor), secure vs non-secure state, PSTATE fields, taking an exception, transitions between 32-bit and 64-bit, reset state, ELRs and SPs by exception level
- Module 10a: Exceptions and Interrupts
- Interrupt controller for single core and MP-core systems, GIC versions, exception and interrupt definitions, synchronous vs asynchronous, precise vs imprecise
- Module 10b: Exceptions and Interrupts
- Taking an exception/interrupt (target exception level?), masking of lower EL interrupts, exception return (ERET instruction), vector table for each EL
- Module 11: Other System Registers
- SCR_EL3, SCTLR_EL3, MDCR_EL3, MIDR_EL1, ID_AA64PFR0_EL1, CLIDR_EL1, CCSIDR_EL1, CSSELR_EL1, ACTRL, AIDR
- Module 12a: Paging (Memory Model)
- Paging concepts, translation look-aside buffer (TLB), AArch64 vs AArch32 memory models, stages of translation, page faults
- Module 12b: Paging (Memory Model)
- TTBR1 and TTBR0, virtual (VA) to physical (PA), virtual to intermediate physical (IPA) to physical, secure EL3 protection, OS page tables, hypervisor page tables, page sizes with 4KB granule (4KB, 2MB, 1GB), page sizes with 16KB granule (16KB, 32MB), page sizes with 64KB granule (64KB, 512MB), 64-bit descriptor format, address translation instructions, TLB maintenance, address space identifier (ASID), virtual machine identifier (VMID)
- Module 13: Caches and Cache Management
- Multi-level cache architecture, cache protocols (MESI and MOESI), coherency, point of unification (PoU), level of unification (LoU), point of coherency (PoC), level of coherency (LoC), instruction cache maintenance, data cache maintenance, cache prefetch, non-temporal accesses
- Module 14: Virtualization
- What virtualization is, hardware partitioning with virtualization, hypervisor configuration register (HCR), virtual interrupt support, virtualization hardware paging
- Module 15: Secure and Non-Secure State
- Non-secure state (normal world) vs secure state (secure world), TrustZone processor and IO devices
- Module 16: Power Management
- Platform power management, individual core power modes (WFI: wait for interrupt, WFE: wait for event, dormant mode, shutdown mode), per core power domains
- Module 17: Debug and Performance Monitors Extension
- Monitor mode (self-hosted), halting debug mode, debug port, trace, external debug entry and exit, performance monitor registers
A La Carte Options
We’re pleased to announce that we also offer the option to customize your own course by purchasing only the modules you need. Expand this section to view the specific topics available. Each topic can be purchased separately, or you can purchase the entire comprehensive course.
 | Course Modules |
| Module | Length | | Module 1: ARM Introduction | 36 minutes | | Module 2: ARMv8-A 64-bit Overview | 49 minutes | | Module 3: Integer (General Purpose) Registers | 44 minutes | | Module 4: Processing Element State (PState) | 28 minutes | | Module 5a: A64 Instructions | 44 minutes | | Module 5b: A64 Instructions | 29 minutes | | Module 6: System Instructions and Calling Conventions | 28 minutes | | Module 7a: Memory Accesses | 43 minutes | | Module 7b: Memory Accesses | 38 minutes | | Module 7c: Memory Accesses | 41 minutes | | Module 8: Floating Point, SIMD and Crypto Extensions | 33 minutes | | Module 9: Exception Levels | 38 minutes | | Module 10a: Exceptions and Interrupts | 35 minutes | | Module 10b: Exceptions and Interrupts | 38 minutes | | Module 11: Other System Registers | 30 minutes | | Module 12a: Paging (Memory Model) | 41 minutes | | Module 12b: Paging (Memory Model) | 56 minutes | | Module 13: Caches and Cache Management | 49 minutes | | Module 14: Virtualization | 37 minutes | | Module 15: Secure and Non-Secure State | 26 minutes | | Module 16: Power Management | 14 minutes | | Module 17: Debug and Performance Monitors Extension | 17 minutes | | |
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