ARM Cortex-M0 and M0+ Hardware Design eLearning Course

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ARM Cortex-M0 and M0+ Hardware Design eLearning Course

Instructor(s): Paul Devriendt
Number of Modules: 26
Subscription Length: 90 days

Course Price
$695.00



ARM Cortex-M0 and M0+ Hardware Design eLearning Course Info

What's Included?

Cortex-M0 & M0+ eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)

You Will Learn:

  • Overview of ARM product line
  • Essentials of the ARM Cortex-M0/M0+ architecture
  • Memory model
  • Core and System Interface architecture
  • How to initialize and debug a core

Course Outline:

  • Module 1: Introduction to ARM
    - ARM the company, ARM the community, processor portfolio, example ARM-based system, evolution of ARM architecture, ARMv7 vs. ARMv8
  • Module 2: ARM Cortex -M0 Overview
    - Cortex-M0 processor diagram, RTL configuration options, integer core pipeline, memory map, register set, program status registers, exceptions and interrupts, power management, debug extensions, documentation
  • Module 3: ARM Cortex -M0+ Overview
    - Cortex-M0+ processor diagram, M0 vs M0+ comparison, core features, exceptions and interrupts, system interfaces, power management, debug extensions, micro trace buffer, RTL configuration options, documentation
  • Module 4: ARMv6-M Programmer's Model
    - Data types, ARM core registers: program counter (PC), link register (LR), stack pointer (SP), PSRs, modes overview, unprivileged vs privileged, stacks, exceptions, instruction sets, branch instructions, data processing instructions, load/store instructions, conditional execution
  • Module 5a: ARMv6-M Memory Model 1
    - System address map, memory segments, system segment, private peripheral bus (PPB) addresses, system control space (SCS) addresses, system control block (SCB) registers, memory types and attributes, endianness, memory barrier instructions: DMB, DSB, instruction synchronization barrier, memory remapping, self modifying code, and more
  • Module 5b: ARMv6-M Memory Model 2
    - System caches, normal memory attributes, device memory and attributes, strongly ordered memory, memory access order, memory ordering restrictions
  • Module 6a: ARMv6-M Exception Handling 1
    - Micro-coded interrupt mechanism, interrupt overheads, exception types, external interrupts, pre-emption, exception model, vector table for ARMv6-M, reset behavior, behavior of all other exceptions, exception priorities, exception states, ISR entry, interrupt stacking, ReturnAddress() values, returning from interrupt, NMI example
  • Module 6b: ARMv6-M Exception Handling 2
    - Nesting example, tail chaining example, late arriving example, supported priority groups, disabling interrupts (priority boosting and PRIMASK), interrupt control and status bits, interrupt sensitivity, vector table in C and Assembly, writing interrupt handlers, internal interrupts, system service call (SVC), priority escalation, fault exceptions on v6-M, precise vs imprecise exceptions, Lockup state
  • Module 7: SysTick Timer
    - SysTick interrupt, related registers, basic operation, calibration, example settings for 25MHz and 14.31MHz
  • Module 8: AHB-Lite
    - Original AHB, AHB-Lite single and multi-layer, inteconnections, basic read, basic write, wait states, HREADY in/out, HTRANS, HBURST, HRESP, ERROR response, locked transfers
  • Module 9: Cortex-M System Design Kit
    - Cortex-M SDK, product overview, AHB components, GPIO, APB components, clocking peripherals sub-systems, multi-master support, behavioral memory models, verification components, AHB memory map, writing code, testbench, simulation, compiling RTL and test code, synthesis, running scripts, documentation
  • Module 10: Cortex-M0 Processor Core
    - Prefetch buffer, hardware multiplier, core pipeline, several examples of instructions flowing through pipeline, execution determinism, instruction cycle timing
  • Module 11: Cortex-M0 System Interfaces
    - Clocks and resets, clock domains, reset timing, AHB-Lite interface and side-band signals, debug interface, power management interface, configuration/status ports
  • Module 12: Cortex-M0 System Integration Example
    - Process level vs. integration level, WIC integration example, integration with a DAP, integration clock gating
  • Module 13: Cortex-M0 System Power Management
    - Architectural Clock Gating (ACG), sleep modes (normal, deep, WIC-based), Wait for Interrupt (WFI), Wait for Event (WFE), power domains (up to 3: always-on, system, debug), state retention power gating
  • Module 14: Cortex-M System Implementation and Integration
    - Development flows, deliverables structure, processor configuration options (ACG, big endian, interrupts, system timers, etc.), clocks and reset, interrupt inputs, integration kit (IK), overview of provided tests, vector capture capabilities of ID, and more
  • Module 15: Cortex-M0 Debug
    - CoreSight, Non-Invasive vs Invasive debug, debug state, debug access port (DAP), ROM tables, breakpoints and watchpoints, data watchpoint and trace (DWT), vector catch, and much more
  • Module 16: Cortex-M0 Initialization
    - Vector table setup, CMSIS, core register access, instruction access, NVIC access functions
  • Module 17: Cortex-M0+ Core
    - Prefetch buffer, hardware multipliers, integer core pipeline with several example of instructions flowing through, IO port, execution determinism, instruction cycle timing
  • Module 18: Cortex-M0+ System Interfaces
    - Clocks and reset, clock domains, clock gating, reset timing, AHB-Lite interface and side-band signals, IO port interface signals, debug interface, power management interface, configuration/status ports
  • Module 19: Cortex-M0+ Memory Protection
    - Default memory map, memory protection overview, region overview, sub-regions, memory types, access permissions, region overlapping, MPU registers
  • Module 20: Cortex-M0+ Integration Example
    - Integration levels, WIC integration example, integration with a DAP, MTB integration example, integration clock gating
  • Module 21: Cortex-M0+ Power Management
    - Architectural Clock Gating (ACG), sleep modes (normal, deep, WIC-based), Wait for Interrupt (WFI), Wait for Event (WFE), power domains, power management units
  • Module 22: Cortex-M0+ Implementation and Intergration
    - Development flows, deliverables structure, clock domain crossing (CDC) paths, processor configuration options (ACG, big endian, interrupts, system timers, etc.), clocks and reset, interrupt inputs, integration kit (IK), overview of provided tests, vector capture capabilities of ID, and more
  • Module 23: Cortex-M0+ Debug
    - CoreSight, Non-Invasive vs Invasive debug, debug state, debug access port (DAP), ROM tables, breakpoints and watchpoints, data watchpoint and trace (DWT), vector catch, and much more
  • Module 24: Cortex-M0+ MTB
    - MTB configuration options, MTB interfaces, MTB operation, trace packet format (I and II), memory model, related registers (POSITION, MASTER, FLOW, BASE, etc.), SRAM memory interface, integration kit, discovery, etc.
Course Modules
ModuleLength
Module 1: Introduction to ARM21 minutes
Module 2: ARM Cortex -M0 Overview24 minutes
Module 3: ARM Cortex -M0+ Overview14 minutes
Module 4: ARMv6-M Programmer's Model48 minutes
Module 5a: ARMv6-M Memory Model 142 minutes
Module 5b: ARMv6-M Memory Model 217 minutes
Module 6a: ARMv6-M Exception Handling 140 minutes
Module 6b: ARMv6-M Exception Handling 243 minutes
Module 7: SysTick Timer13 minutes
Module 8: AHB-Lite24 minutes
Module 9: Cortex-M System Design Kit21 minutes
Module 10: Cortex-M0 Processor Core22 minutes
Module 11: Cortex-M0 System Interfaces15 minutes
Module 12: Cortex-M0 System Integration Example8 minutes
Module 13: Cortex-M0 System Power Management14 minutes
Module 14: Cortex-M System Implementation and Integration25 minutes
Module 15: Cortex-M0 Debug35 minutes
Module 16: Cortex-M0 Initialization10 minutes
Module 17: Cortex-M0+ Core23 minutes
Module 18: Cortex-M0+ System Interfaces16 minutes
Module 19: Cortex-M0+ Memory Protection20 minutes
Module 20: Cortex-M0+ Integration Example5 minutes
Module 21: Cortex-M0+ Power Management14 minutes
Module 22: Cortex-M0+ Implementation and Intergration39 minutes
Module 23: Cortex-M0+ Debug27 minutes
Module 24: Cortex-M0+ MTB19 minutes