- Module 1: Introduction
Intro to ARM architecture profiles v7-A and v8-A, intro to v7-A 32-bit processors and v8-A 64-bit processors
- Module 2: Pipeline ARM Cortex-A57
Covers overview of Cortex-A57, MPCore and clusters, main implementation options, block diagram, level 2 memory system, cache and TLBs, pipeline stages with descriptions, execution clusters, L2 cache organization, AMD Opteron A1100 (Seattle) coverage, AMD Seattle: SoC, security info, I/O structure, SCP internals, SCP boot flow, DRAM info
- Module 3: Pipeline ARM Cortex-A72
Covers overview of Cortex-A72, cluster and cores, implementation options, block diagram, pipeline stages with descriptions, load/store, level 2 memory system
- Module 4: Pipeline ARM Cortex-A53
Covers overview of Cortex-A53, MPCore and clusters, block diagram, TLBs, level 2 memory system, L1 data cache, L1 instruction cache, L2 cache, pipeline stages with descriptions, branch prediction, power management
- Module 5: AppliedMicro X-Gene
Covers overview of AppliedMicro X-Gene, roadmap, X-Gene1 (execution and IO), X-Gene2 (processor module and execution), X-Gene3 intro
- Module 6: Interconnects
Covers overview of AMBA5 - CHI (coherent hub interconnect), importance of the interconnect, role of the interconnect, CoreLink CCN-504 CHI, receive and transmit, CCN-504 and CCN-508 Rings, layers and nodes, system address map, performance analysis
