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ARM v8-A Memory Management eLearning Course
Instructor(s): Paul Devriendt
Number of Modules: 6
Subscription Length: 90 days
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Course Price
$395.00 |
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ARM v8-A Memory Management eLearning Course Info
What's Included?
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ARMv8-A eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
A La Carte Course:
This eLearning course is a subset of the comprehensive ARM 64-bit Architecture (ARM v8-A) eLearning course. If you want or need the full, comprehensive course, please visit that page.
Course Outline:
- Module 7a: Memory Accesses
- Load/Store architecture, addressing modes, load/store indexing and auto incrementing, multi-register loads/stores, little endian vs big endian, data alignment, instruction alignment, unaligned (misaligned) accesses
- Module 7b: Memory Accesses
- Accessing devices with memory instructions, memory types and rules, domains (NSH: non-shareable, ISH: inner shareable, OSH: outer-shareable, SY: full system), memory coherency, weakly ordered, memory barrier instructions (DMB: data memory barrier, DSB: data synchronization barrier, ISB: instruction synchronization barrier), JIT / self-modifying code
- Module 7c: Memory Accesses
- Device memory attributes (gathering, reordering, early write acknowledgement hint), memory access restrictions, semaphore flow, semaphore instructions, load-acquire and store-release, non-temporal load/store
- Module 12a: Paging (Memory Model)
- Paging concepts, translation look-aside buffer (TLB), AArch64 vs AArch32 memory models, stages of translation, page faults
- Module 12b: Paging (Memory Model)
- TTBR1 and TTBR0, virtual (VA) to physical (PA), virtual to intermediate physical (IPA) to physical, secure EL3 protection, OS page tables, hypervisor page tables, page sizes with 4KB granule (4KB, 2MB, 1GB), page sizes with 16KB granule (16KB, 32MB), page sizes with 64KB granule (64KB, 512MB), 64-bit descriptor format, address translation instructions, TLB maintenance, address space identifier (ASID), virtual machine identifier (VMID)
- Module 13: Caches and Cache Management
- Multi-level cache architecture, cache protocols (MESI and MOESI), coherency, point of unification (PoU), level of unification (LoU), point of coherency (PoC), level of coherency (LoC), instruction cache maintenance, data cache maintenance, cache prefetch, non-temporal accesses
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| Module | Length | | Module 7a: Memory Accesses | 43 minutes | | Module 7b: Memory Accesses | 38 minutes | | Module 7c: Memory Accesses | 41 minutes | | Module 12a: Paging (Memory Model) | 41 minutes | | Module 12b: Paging (Memory Model) | 56 minutes | | Module 13: Caches and Cache Management | 49 minutes | | |
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