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ARMv8-M and v8.1-M eLearning Course
Instructor(s): Paul Devriendt
Number of Modules: 61
Subscription Length: 90 days
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Course Price
$895.00 |
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ARMv8-M and v8.1-M Architecture
What's Included?
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ARMv8-M and v8.1-M eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
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Who Should View?
This course is aimed at software developers and system architects developing for systems powered by ARMv8-M processors, such as the Cortex-M23 and the Cortex-M33 processors. It is relevant for operating system development, device driver development, low-level coding and security firmware, and for validation and debug.
Course Outline:
- Module 1: Introduction to ARM and v8-M
- Introduction to ARM, ARM profiles and terminology
- Module 2: ARM v8-M Basics
- Block diagram walk-through of example Cortex-M23 system, thread mode vs handler mode, security states (TrustZone)
- Module 3: ARM Instruction Sets
- ARM instructions, Thumb instructions, Thumb2 (T32), instruction fetching, interworking intro
- Module 4a: Base Register Set (Integer Registers)
- General purpose (integer) registers, instruction register encoding, R13 (SP), R15 (PC), register protection, special purpose registers
- Module 4b: Base Register Set (Integer Registers)
- XPSR, APSR, NZCV values, IPSR, EPSR, CONTROL register, RETPSR, MSPLIM and PSPLIM
- Module 5: Other Important Registers
- SCR, IARCR
- Module 6: T32 Instruction Set
- Baseline vs Mainline, data processing instructions, use of Flags, using low registers, bit manipulation, constants, multiply and divide
- Module 7: Saturating Instructions
- Saturation explained, USAT and SSAT
- Module 8a: Branching Instructions
- B and B<condition>, branch ranges, narrow vs wide branch, aligning target address, BL (branching to a subroutine), BX (branching to an address), LR spill to stack, BLX (branching to a subroutine at an address), reserved register for branching
- Module 8b: Branching Instructions
- Interstating (BXNS and BLXNS), CBNZ and CBZ, Table branch (TBB and TBH), using LDM, condition execution (IT), exception - continuable instructions, resume vs restart
- Module 9: Branching Instructions - v8.1 Enhancements
- Low overhead loop, branch future (BF), conditional instructions, CINC
- Module 10: More Instructions
- Supervisor call (SVC), no operation (NOP), BKPT (breakpoint), semi-hosting
- Module 11: ACLE - ARM C Language Extensions
- C vs assembler, extensions (macros, intrinsics, etc.)
- Module 12: Coprocessor Support
- Intro and purpose of coprocessors, external coprocessor interface, data transfers, instructions mechanism, FPU example
- Module 13a: Memory
- Word terminology, memory mapped architecture, memory regions, accesses, load-store architecture, memory types, non-posted info
- Module 13b: Memory
- Addressing modes, aligned vs misaligned accesses and rules, stack alignment
- Module 13c: Memory
- Little-endian vs Big-endian, 2-byte vs 4-byte Thumb instructions and endianess, LDM and STM, LDRT and STRT
- Module 14: Memory Type
- Normal memory vs device memory, device memory attributes (gathering, reordering, early termination), valid combinations of attributes, system address map and regions, system control space (SCS)
- Module 15: Memory Ordering and Barriers
- Memory types and observers, shareability domains, weak ordering, memory barrier instructions (DMB, DSB and ISB), barriers and code portability
- Module 16: LoadAcquire and StoreRelease
- Load-Acquire and Store-Release examples
- Module 17: Semaphores
- Exclusive monitors, exclusive reservation granules, exclusive instructions, semaphore flow example, exclusive and power management
- Module 18a: MPU - Memory Protection Unit
- MPU purpose, MPU components: Security Attribution Unit (SAU), Implementation-defined Attribution Unit (IDAU), MPU-Secure and MPU-Non-secure
- Module 18b: MPU - Memory Protection Unit
- Single region match, overlapping regions (not supported), crossing boundaries, use of background region, MemManage fault, MPU_CTRL (control register), MPUT_TYPE (type register)
- Module 19: MPU Setup
- Accessing the MPU base/limit registers, MPU_RNR (region number register), MPU_RBAR (base address register), MPU_RLAR (limit address register), MPU_MAIR0/1 (attribute registers), attribute encodings, default memory map Cortex-M23 and -M33
- Module 20: The Stack
- Stack implementation (full descending), stack selection, stack limits
- Module 21a: Caches
- Purpose of and need for caches, cache alternative: TCM (Tightly Coupled Memory), cache basics (cache line, cache tag, cache way, cache index), full vs set associativity
- Module 22b: Caches
- Cache line state (clean vs dirty, shared vs exclusive, etc.), management of coherency, Point of Unification (PoU), Point of Coherency (PoC), CLIDR (cache level ID register), CCR (Configuration and Control register), cacheability of normal memory type, behavior of disabled caches, MPU and caches, cache preload, cache maintenance instructions, self-modifying code affects, TrustZone and caches (HW tracking vs not)
- Module 22: TCM - Tightly Coupled Memory
- TCM purpose and example implementation
- Module 23a: Exceptions
- Faults and interrupts, thread mode vs handler mode, privileged and unprivileged execution, exceptions and TrustZone
- Module 23b: Exceptions
- Exception states (inactive, pending, active, active and pending), individual interrupt control, synchronous vs asynchronous exceptions, precise vs imprecise exceptions, exceptions and priority, pre-emption, external interrupt delivery (NVIC)
- Module 24a: Exceptions - The Vector Table
- Intro to the vector table, reset behavior, mainline vs baseline, external interrupt, SysTick, SVCall and PendSV, Debug
- Module 24b: Exceptions - The Vector Table
- SecureFault, UsageFault, BusFault, MemManageFault, HardFault, NMI, interrupts and NMI, reset, warm reset, fault status registers
- Module 25: Exception Handling
- Register stacking, LR magic values (EXC_RETURN), exception return
- Module 26a: Exception Priorities
- Baseline exception numbers and priorities, Mainline exception numbers and priorities, PRIGROUP values
- Module 26b: Exception Priorities
- Escalation to HardFault, Lockup, numerous interrupt examples, priority control, BASEPRI, PRIMASK, FAULTMASK
- Module 27: Exception Control
- Individual interrupt control (enable, disable, clear pending, set pending, active), STIR (software triggered interrupt register), SHCSR (system handler control and status register)
- Module 28: Exception - Additional Details
- Long running instructions, access to IO devices, instruction restart vs resume, SVC instruction, PendSV info and example,
- Module 29: SysTick - System Timer
- Purpose and use, SYST_CSR (control and status register), related registers (e.g. calibration, reload, current value, etc.)
- Module 30: DSP Extension
- Digital signal processing intro, use with CMSIS DSP library
- Module 31: Floating-point (FP) Extension
- Intro to floating-point (IEEE-754, single-precision, double-precision, half-precision), related registers (s0-s31 and d0-d31), parameter passing options, FPCSR (floating-point control and status register), VMSR instruction
- Module 32: Security Extension (TrustZone) Introduction
- TrustZone vs SecurCore, intro to TrustZone, limitations, secure side is typically small
- Module 33: Security Extension (TrustZone) Concepts
- Quick walk-through of ARMv8-A TrustZone to illustrate concepts, ARMv8-M TrustZone elements (e.g. memory protection)
- Module 34: Security Extension (TrustZone) Registers
- Security states, banked registers, banked stack pointers, information leakage
- Module 35a: Security Extension (TrustZone) Security By Address
- Address types, Not-NSC, shared data buffers (and related cache issues)
- Module 35b: Security Extension (TrustZone) Security By Address
- MPU, SAU and IDAU elements, current execution state, access violations, SAU (Security Attribution Unit), IDAU (Implementation-defined Attribution Unit), exempt address ranges
- Module 36a: Security Extension (TrustZone) Cross Domain Switching - Code
- Cross domain switching intro and examples, SG (secure gateway), security checks, calling within the secure region, info related to BXNS
- Module 36b: Security Extension (TrustZone) Cross Domain Switching - Code
- Another cross domain switching example, magic return address, integrity signature, Unprivileged - PXN (new with v8.1-M)
- Module 37a: Security Extension (TrustZone) Interrupts
- Banking and exceptions, target security state, vector table (VTOR), SecureFault, exception handlers, stacked registers
- Module 37b: Security Extension (TrustZone) Interrupts
- Numerous examples of exceptions / interrupts, issues related to TrustZone, exception priority and issues
- Module 38: Security Extension (TrustZone) Summary of New Instructions
- SG (secure gateway), interstating (BXNS and BLXNS), MOVW and MOVT background info, the problem and solution, execute only memory, TT (test target)
- Module 39: TrustZone and FPU
- ACLE and FPU status / control register, v8.1M additions related to FPCSR
- Module 40: M-profile Vector (MVE) Extension
- Helium intro, configuration options, extended register bank (S registers, D registers and Q registers), v8.1M enhancements to FPCSR
- Module 41: Incompatibilities from v6M and v7M
- Bit banding, stack alignment, memory protection, vector table, EXC_RETURN, DSB and SCS, TrustZone, Debug and Trace
- Module 42: RAS Extension
- Reliability Availability Serviceability intro, data poisoning example
- Module 43: Debug
- Intro to debug of embedded systems, trace (non-invasive) vs debug (invasive), security and debug, Cortex-M33 debug components, BPU (breakpoint unit), halting debug mode, monitor debug mode, GDBServer, DWT (watchpoints), performance monitoring (v8.1M), ETM (embedded trace macrocell), MTB (MicroTrace Buffer), semi-hosting, v8.1M unprivileged debug extension
- Module 44: Software Tools
- Non-secure code and veneers CMSIS, calling conventions (ABIs)
- Module 45: AHB5
- AMBA intro, bridge to APB, AHB observations, AHB5 master and slave output signals
- Module 46: Power Management
- WFI (wait for interrupt instruction), sleep on exit, WFE (wait for event instruction), event register, wakeup interrupt controller, power management and TrustZone
- Module 47: ARM Processor Implementations
- ARMv6-M and ARMv7-M processors vs ARMv8-M processors, Fetch- > Decode > Execute (pipeline), execution predictability
- Module 48: ARM Cortex-M23 Processor
- Overview, configuration options, functional blocks, memory model, default memory map
- Module 49: ARM Cortex-M33 Processor
- Overview, configuration options, functional blocks, memory model, default memory map
 | Course Modules |
| Module | Length | | Module 1: Introduction to ARM and v8-M | 36 minutes | | Module 2: ARM v8-M Basics | 27 minutes | | Module 3: ARM Instruction Sets | 36 minutes | | Module 4a: Base Register Set (Integer Registers) | 35 minutes | | Module 4b: Base Register Set (Integer Registers) | 33 minutes | | Module 5: Other Important Registers | 15 minutes | | Module 6: T32 Instruction Set | 31 minutes | | Module 7: Saturating Instructions | 4 minutes | | Module 8a: Branching Instructions | 43 minutes | | Module 8b: Branching Instructions | 27 minutes | | Module 9: Branching Instructions - v8.1 Enhancements | 34 minutes | | Module 10: More Instructions | 20 minutes | | Module 11: ACLE - ARM C Language Extensions | 10 minutes | | Module 12: Coprocessor Support | 14 minutes | | Module 13a: Memory | 26 minutes | | Module 13b: Memory | 18 minutes | | Module 13c: Memory | 25 minutes | | Module 14: Memory Type | 30 minutes | | Module 15: Memory Ordering and Barriers | 26 minutes | | Module 16: LoadAcquire and StoreRelease | 6 minutes | | Module 17: Semaphores | 24 minutes | | Module 18a: MPU - Memory Protection Unit | 21 minutes | | Module 18b: MPU - Memory Protection Unit | 18 minutes | | Module 19: MPU Setup | 23 minutes | | Module 20: The Stack | 11 minutes | | Module 21a: Caches | 22 minutes | | Module 21b: Caches | 42 minutes | | Module 22: TCM - Tightly Coupled Memory | 5 minutes | | Module 23a: Execptions | 18 minutes | | Module 23b: Exceptions | 24 minutes | | Module 24a: Exceptions - The Vector Table | 23 minutes | | Module 24b: Exceptions - The Vector Table | 33 minutes | | Module 25: Exception Handling | 29 minutes | | Module 26a: Exception Priorities | 21 minutes | | Module 26b: Exception Priorities | 26 minutes | | Module 27: Exception Control | 13 minutes | | Module 28: Exception - Additional Details | 19 minutes | | Module 29: SysTick - System Timer | 9 minutes | | Module 30: DSP Extension | 4 minutes | | Module 31: Floating-point (FP) Extension | 17 minutes | | Module 32: Security Extension (TrustZone) Introduction | 11 minutes | | Module 33: Security Extension (TrustZone) Concepts | 11 minutes | | Module 34: Security Extension (TrustZone) Registers | 13 minutes | | Module 35a: Security Extension (TrustZone) Security by Address | 11 minutes | | Module 35b: Security Extension (TrustZone) Security by Address | 14 minutes | | Module 36a: Security Extension (TrustZone) Cross Domain Switching - Code | 17 minutes | | Module 36b: Security Extension (TrustZone) Cross Domain Switching - Code | 16 minutes | | Module 37a: Security Extension (TrustZone) Interrupts | 18 minutes | | Module 37b: Security Extension (TrustZone) Interrupts | 10 minutes | | Module 38: Security Extension (TrustZone) Summary of new Instructions | 9 minutes | | Module 39: TrustZone and FPU | 3 minutes | | Module 40: M profile Vector (MVE) Extension | 11 minutes | | Module 41: Incompatibilities from v6M and v7M | 11 minutes | | Module 42: RAS Extension | 7 minutes | | Module 43: Debug | 33 minutes | | Module 44: Software Tools | 6 minutes | | Module 45: AHB5 | 14 minutes | | Module 46: Power Management | 9 minutes | | Module 47: ARM Processor Implementations | 6 minutes | | Module 48: ARM Cortex-M32 Processor | 10 minutes | | Module 49: ARM Cortex-M32 Processor | 12 minutes | | |
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