Advanced PCIe eLearning Course

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Comprehensive PCIe 5.0 eLearning Course
Advanced PCIe eLearning Course
Core PCIe eLearning Course
Fundamentals of PCI Express eLearning Course
Intro to PCI Express IO Virtualization eLearning Course
PIPE 6.0 - PHY Interface for PCI Express and more
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Advanced PCIe eLearning Course

Instructor(s): Joe Winkles
Number of Modules: 32
Subscription Length: 90 days

Course Price
$895.00
Bundle Price (Course & Arbor)
$1,295.00
(more info on Arbor)



 Advanced PCI Express 3.x, 4.0 & 5.0 (w/ PIPE) eLearning Course Info

 Note: This course is a subset of the Comprehensive PCIe 5.0 eLearning course.

What's Included?

Advanced PCI Express 3.x, 4.0 & 5.0 eLearning modules and PIPE 6.0 eLearning Modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)
PCI Express eBook
(yours to keep, does not expire)

Benefits of eLearning:

  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course

You Will Learn:

  • PCI Express features and capabilities
  • The definition and responsibilities of each of the layers in the interface
  • Physical Layer changes to support PCIe Gen3, Gen4 and Gen5 such as 128b/130b and Tx Equalization
  • The link training process including changes made in rev 5.0 spec such as Alternate Protocol Negotiation
  • The purpose of equalization and how it is done in PCIe 3.0 and later
  • Features added to Rev 4.0 and Rev 5.0 spec such as Lane Margining, Retimers, System Firmware Intermediary


If you already understand PCIe protocol as described in the rev 2.0 specification and you need to understand spec additions from spec rev 3.0 onwards, this is the course to take. To serve as a refresher, the course starts with a high-level view of the design to provide the big-picture context. The course then drills down into design updates associated with Gen3, Gen4 and Gen5. We cover topics such as 128b/130b, Retimers, Lane Margining etc.

Who Should View?

This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers.

Advanced PCIe Module Descriptions:

  • Module 1: PCIe Review and new features
    - Introduction to PCIe speed changes, new and expanded fields of TLPs (e.g. 10-bit Tags, deferred memory writes) and coverage of extended MSI data field in interrupts
  • Module 2: Scaled Flow Control
    - Review of normal flow control, introduction of scaled flow control, motivation for scaled flow control, new Data Link Feature DLLPs, updates to DLCMSM state machine, example credit exchange with scaled flow control
  • Module 3: New DLLPs and Ack/Nak Changes
    - Introduction of new DLLPs, review of the Ack / Nak protocol, updates to the Replay Timer (simplified replay timer limit)
  • Module 4a: Physical Layer: Logical (128b/130b)
    - Byte striping, scrambling, 128/130b, packet encapsulation
  • Module 4b: Physical Layer: Logical (128b/130b)
    - Byte striping, scrambling, 128/130b, packet encapsulation
  • Module 5: Physical Layer: Electrical
    - High-speed signaling, differential signals, ISI, de-emphasis, equalization, eye diagrams
  • Module 6a: Link Initialization and Training
    - LTSSM(Detect, Polling, Configuration, Recovery), link and lane numbering, speed change
  • Module 6b: Link Initialization and Training
    - Equalization procedure, dynamic link width changes, loopback, etc.
  • Module 7: Power Management
    - Device power states (D0, D1, D2, D3), link power states (L0, L0x, L1, L2, L2/L3 Ready, L3), Active State Power Management (ASPM), Software power management, power management events (PME), Dynamic Power Allocation (DPA), Optimized Buffer Flush Fill (OBFF), Latency Tolerance Reporting (LTR)
  • Module 8: Retimers
    - Intro to Retimers, definition of link segments and pseudo-ports, forwarding mode and execution mode, what retimers can modify, handling electrical idle, handling training of links (and link segments) with a focus on Tx equalization
  • Module 9: Lane Margining
    - Intro to lane margining, time margining concept, voltage margining concept, Lane Margining Extended Capability structure, initiating margining commands, performing lane margining on a retimer (Control SKP ordered sets)
  • Module 10: Flattening Portal Bridges (FPB)
    - Static allocation limits, removing the designated bus number within a switch, dynamic allocation limits, FPB Routing ID vector and FPB Memory routing vector, solution for hot plug environments
  • Module 11: Hierarchy ID, DVSEC, Enhanced Allocation and Emergency Power Reduction
    - Intro to Hierarchy ID messages and capability structure, intro to Designated Vendor-Specific (DVSEC) feature, intro to Enhanced Allocation feature (for embedded environments), intro to Emergency Power Reduction State
  • Module 12: System Firmware Intermediary (SFI)
    - Choosing to notify firmware or the OS
  • Module 13: Downstream Port Containment (DPC and eDPC)
    - Handling of events that should be isolated
  • Module 14: Multi-Casting
    - What it is and how it works
  • Module 15: Protocol Multiplexing
    - An optional feature allowing other protocols to simultaneously share the PCIe link
  • Module 16: TLP Processing Hints and Steering Tags
    - Describes the TLP fields involved and how the Root Complex interprets them
  • Module 17: Alternative Routing-ID Interpretation (ARI)
    - Describes the purpose of ARI and affects it may have in a system
  • Module 18: Atomic Operations
    - Covers the different atomic ops supported in PCIe
  • Module 19: Resizable BARs
    - Provides background for the purpose of resizable BARs and how they
  • Module 20: L1 Substates
    - Goes through this important addition to link power management
  • Module 21: Lightweight Notification
    - Provides context of why this can be useful for caching data in a PCIe function and how it works
  • Module 22: Process Address Space ID (PASID)
    - Provides a brief into to the main uses of PASID with IOMMUs
  • Module 23: Precision Time Measurement (PTM)
    - Goes over the mechanism to share a common time domain with very tight timing requirements in PCIe systems
  • Module 24: Device Readiness Status (DRS) and Function Readiness Status (FRS)
    - Talks about the purpose of this feature

PIPE 6.0 Module Descriptions:

  • Module 1: Introduction
    - Intro to PIPE, Original PIPE vs SerDes PIPE, PCLK options, data throttling, Message Bus intro, interface types (legacy vs low pint count, LPC), registers in MAC and PHY, combining PIPEs for multi-lane link
  • Module 2a: PHY/MAC Interface (Intro)
    - Interface support options, Short-Reach (SR) applications, terminology of signal names in spec
  • Module 2b: PHY/MAC Interface (Common Signals)
    - External signals, command signals, command interface inputs to PHY, SRIS motivation, power states, receiver detection, command interface status outputs, PHY status signals (inputs and output), data signal, block synchronization, original PIPE block diagrams
  • Module 2c: PHY/MAC Interface (Original and SerDes specific signals)
    - SerDes signals, original PIPE signals, Message Bus, Message Bus commands, command formats, Message Bus rules
  • Module 3: PHY Registers
    - PHY register list, register definitions, register groups, intro to equalization, PCIe EQ starting parameters, delivering Tx FS/LF values, speed change example, getting local coefficients example, updating PHY Tx values
  • Module 4: MAC Registers
    - Elastic buffer registers, signal integrity, PHY recalibration, link equalization evaluation, Gen5 Tx parameters, local preset values, Gen3 and Gen4 Tx parameters
  • Module 5: PIPE Operational Behavior: PCIe Mode
    - Key features, voltage margining, Tx options (e.g. low voltage), de-emphasis intro and setting de-emphasis value, Inter-Symbol Interference (ISI)
  • Module 6a: Equalization Process
    - Equalization commonalities across protocols, 3-tap equalizer, preset encodings, effect of Tx equalization, location of EQ circuitry and logic, initializing preset values, fetching PHY Tx values for preset(s), Tx equalizer values, relationship between coefficients and FS, MAC tells PHY what coefficients to use, MAC applies coefficients
  • Module 6b: Equalization Process
    - Equalization phase summary, EQ phase 1 step through, EQ phase 2 step through, accepting vs rejecting coefficients, EQ phase 3 step through, Tx EQ finishing, Rx equalization
  • Module 7: PCIe Lane Margining
    - Lane margining background, time margining concept, voltage margining concept, SW in control of margining, related configuration registers for PCIe, location of config space, margining register encodings for PCIe, determining what's an error, step time margin command, step voltage margin command, step margin command response, dependent vs independent samplers, affected PHY registers, margining a retimer, receiver numbers, affected MAC registers
  • Module 8: PCIe Elastic Buffer
    - Purpose of elastic buffer, nominal half-full buffer, adding / removing SKPs (skips), nominal empty buffer, PHY elastic buffer registers
  • Module 9: PCIe Power States
    - Intro to power states, timing diagrams for L0 to L0s entry and exit, timing diagram for L0 to L1 entry and exit, L1 substates, receiving electrical idle
  • Module 10: PIPE Operational Behavior: USB Mode
    - Key features, USB power states, low frequency periodic signaling (LFPS), variants of LFPS, receiver detection, USB equalization, forcing compliance patterns
  • Module 11: PIPE Operational Behavior: SATA Mode
    - Key features, Out of Band (OOB) signaling, OOB and alignment, SATA speed negotiation, SATA power states
Course Modules
ModuleLength
Module 1: Introduction12 minutes
Module 2a: Architecture Overview 33 minutes
Module 2b: Architecture Overview 33 minutes
Module 2c: Architecture Overview 28 minutes
Module 3: 10-bit Tags and Extended MSI Data27 minutes
Module 4: Scaled Flow Control38 minutes
Module 5: New DLLPs and Ack/Nak Changes22 minutes
Module 12a: Physical Layer: Logical (128b/130b) 28 minutes
Module 12b: Physical Layer: Logical (128b/130b) 27 minutes
Module 12c: Physical Layer: Logical (128b/130b) 22 minutes
Module 12d: Physical Layer: Logical (128b/130b) 35 minutes
Module 12e: Physical Layer: Logical (128b/130b) 26 minutes
Module 13a: Physical Layer: Electrical 41 minutes
Module 13b: Physical Layer: Electrical 33 minutes
Module 13c: Physical Layer: Electrical 38 minutes
Module 14a: Link Initialization and Training (LTSSM) 23 minutes
Module 14b: Link Initialization and Training (LTSSM) 29 minutes
Module 14c: Link Initialization and Training (LTSSM) 29 minutes
Module 14d: Link Initialization and Training (LTSSM) 31 minutes
Module 14e: Link Initialization and Training (LTSSM) 33 minutes
Module 14f: Link Initialization and Training (LTSSM) 49 minutes
Module 14g: Link Initialization and Training (LTSSM) 31 minutes
Module 14h: Link Initialization and Training (LTSSM) 15 minutes
Module 17a: Power Management 28 minutes
Module 17b: Power Management 49 minutes
Module 19: Retimers 51 minutes
Module 20: Lane Margining 59 minutes
Module 21: Flattening Portal Bridge (FPB) 25 minutes
Module 22: Heirarchy ID, DVSEC, Enhanced Allocation and Emergency Power Reduction 23 minutes
Module 23: System Firmware Intermediary Support 39 minutes
Module 24a: Downstream Port Containment (DPC) 27 minutes
Module 24b: Downstream Port Containment (DPC) 17 minutes