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CXL 3.1 Update eLearning Course Info
What's Included?
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CXL 3.1 Update eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
You Will Learn:
- 256 Byte Flit Mode
- Port-Based Routing
- Cache.mem Back-Invalidations
- CXL Fabric extensions
- and much more...
Who Should View?
This course is for anyone who has a solid understanding of CXL 2.0 and would like to quickly get up-to-speed on CXL 3.1.
Course Outline:
- Module 1: Course Intro
- Introduction to the course and explanation of what is covered
- Modules 2a-2f: Features and Architecture Overview
- Introduces new features added with 3.0 and 3.1: 256B Flits, PAM4 with PCIe6, Hierarchy-Based Routing (HBR) vs Port-Based Routing (PBR), CXL.mem Back-Invalidation, Multi-Headed (MH) Memory Devices, Fabric Attached Memory (FAM), CXL Fabric, CXL Device Scaling, Host Physical Address space vs Device Physical Address space, Dynamic Capacity Device, Device Media Partition, G-FAM Access Endpoint, Global Integrated Memory, a review of the CXL Port Layer architecture and discussion of updates with CXL 3.x
- Modules 3a-3d: Transaction Layer: CXL.mem Protocol
- Reviews the CXL.mem protocol from 2.0 and prior and then discusses the new features added with 3.x and walks through examples; this includes back invalidations, 256B flits, new fields in requests and responses, Host to Device bias flip for HDM-D, and more
- Modules 4a-4b: Transaction Layer: CXL.cache Protocol
- Reviews the CXL.cache protocol and then discusses new fields in requests for features like Packet-Based Routing, Logical Cache IDs, etc.; Walks through numerous examples of snooping caches
- Module 5: Transaction Layer: CXL.io Protocol and Transaction Ordering Rules
- Discusses additions to the PCIe protocol to support new CXL features; also describes the ordering rules of CXL and how those are impacted with CXL 3.x
- Modules 6a-6b: Link Layer
- Presents the differences between 68B and 256B flits for packing with CXL.io traffic, lots of discussion around 256B flit mode with CXL.cachemem flit packing
- Module 7: ARB / MUX Layer
- Reviews vLSMs (Virtual Link State Machines) and the new states added with CXL 3.0, how 256B flits affects behavior of power management, L0p support, ALMP flit format in 256B flit mode
- Modules 8a-8b: Logical Physical Layer
- Provides a detailed description of 256B flit mode and then walks through updates to the Link Training and Status State Machine (LTSSM) including the behavior in 1b/1b mode, shows ordered set differences at all speeds
- Module 9: Enumeration and Manageability
- Discusses a new level of memory interleaving, Dynamic Capacity Devices (DCDs), their purpose and behavior
- Module 10: Control and Status Registers
- Walks through important updates and additions to CXL-related registers to support the new features and behaviors of CXL 3.x
- Modules 11a-11c: Switches
- Describes numerous example topologies of fabric systems with switches and the various types of devices that can be connected; routing of traffic through switches, address translation process, protections that can be implemented, differences between different types of devices (e.g. LD-FAM vs G-FAM), Global Integrated Memory (GIM), switch back-invalidation support, switch cache device scaling support and finally a mention of the Fabric Manager (FM) APIs
 | Course Modules |
| Module | Length | | Module 1: Course Intro | 22 minutes | | Module 2a: Features and Architecture Overview | 23 minutes | | Module 2b: Features and Architecture Overview | 22 minutes | | Module 2c: Features and Architecture Overview | 41 minutes | | Module 2d: Features and Architecture Overview | 56 minutes | | Module 2e: Features and Architecture Overview: CXL Port Layer Architecture | 29 minutes | | Module 2f: Features and Architecture Overview: Transaction Flow Models | 22 minutes | | Module 3a: Transaction Layer: CXL.mem Protocol | 47 minutes | | Module 3b: Transaction Layer: CXL.mem Protocol | 50 minutes | | Module 3c: Transaction Layer: CXL.mem Protocol | 31 minutes | | Module 3d: Transaction Layer: CXL.mem Protocol | 58 minutes | | Module 4a: Transaction Layer: CXL.cache Protocol | 33 minutes | | Module 4b: Transaction Layer: CXL.mem Protocol | 25 minutes | | Module 5: Transaction Layer: CXL.io Protocol and Transaction Ordering Rules | 33 minutes | | Module 6a: Link Layer | 62 minutes | | Module 6b: Link Layer | 56 minutes | | Module 7: ARB / MUX Layer | 31 minutes | | Module 8a: Logical Physical Layer | 37 minutes | | Module 8b: Logical Physical Layer: Link Training and Alternate Mode Negotiation | 40 minutes | | Module 9: Enumeration and Manageability | 43 minutes | | Module 10: Control and Status Registers | 19 minutes | | Module 11a: Switches | 63 minutes | | Module 11b: Switches | 67 minutes | | Module 11c: Switches | 69 minutes | | |
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