CXL Fundamentals eLearning Course

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CXL Fundamentals eLearning Course

Instructor(s): Ravi Budruk
Number of Modules: 15
Subscription Length: 90 days

Course Price
$595.00



CXL Fundamentals eLearning Course Info

What's Included?

CXL eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)

Benefits of eLearning:

  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course

You Will Learn:

  • CXL system architectures with Type 1, Type 2 and Type 3 devices
  • CXL Port Layers with an overview of each
  • Intro to DVSEC and Component Register Space for CXL

Who Should View?

This course is perfect for anyone wanting a good overview of the capabilities of Compute Express Link (CXL) and the problems it can help solve.

Course Outline:

  • Module 1: Introduction and Outline
    - Intro to the course, outline and objectives
  • Module 2a: Features and Architecture Overview
    - Intro to CXL features and device types
  • Module 2b: Features and Architecture Overview
    - Description of the CXL Flex Bus Port
  • Module 2c: Features and Architecture Overview
    - Example system with CXL Type 2 device, low latency focus and CXL 2.0 vs CXL 1.1
  • Module 3: CXL Port Layer Architecture
    - Port layered architecture, intro to Transaction Layer, Link Layer, ARB/Mux Layer and Physical Layer as well as CXL Flits
  • Module 4: CXL Transaction Flow: PCIe Devices
    - Shows traditional transaction flows of PCIe devices both with and without Private Device Memory (PDM)
  • Module 5a: CXL Transaction Flow: Type 3 Devices
    - Discusses Type 3 devices as a memory buffer / expander including how it fits in a system's address map
  • Module 5b: CXL Transaction Flow: Type 3 Devices
    - Introduces CXL 2.0 with switches and Multi-Logical Devices (MLD)
  • Module 6: CXL Transaction Flow: Type 1 Devices
    - Discusses transaction flows and requirements for Type 1 devices and what can be cached where
  • Module 7a: CXL Transaction Flow: Type 2 Devices
    - Discusses transaction flows of Type 2 devices and the device characteristics
  • Module 7b: CXL Transaction Flow: Type 2 Devices
    - Shows example platform address map with Type 2 CXL devices, discusses host bias versus device bias modes
  • Module 7c: CXL Transaction Flow: Type 2 Devices
    - Walks through a transaction flow and CXL's asymmetric coherence protocol
  • Module 8: Transaction Layer Overview
    - Goes through CXL.mem protocol examples with Type 2 and Type 3 devices, also goes through various CXL.cache examples
  • Module 9: Link Layer and ARB/MUX Layer Overview
    - CXL.io Link Layer, Flit packing, introduces CXL.cache / CXL.mem protocol flit and CXL.cache / CXL.mem all-data flit, CXL ARB/Mux Layer protocol mux-ing / demux-ing; Flex Bus physical layer overview; byte striping in 128b/130b mode; Sync Header Bypass Mode (Latency Optimized Mode)
  • Module 10: DVSEC and Component Register Space Overview
    - Introduces configuration space related registers, DVSEC descriptions, CXL 1.1 and CXL 2.0 memory mapped registers
Course Modules
ModuleLength
Module 1: Introduction and Outline15 minutes
Module 2a: Features and Architecture Overview19 minutes
Module 2b: Features and Architecture Overview16 minutes
Module 2c: Features and Architecture Overview36 minutes
Module 3: CXL Port Layer Architecture39 minutes
Module 4: CXL Transaction Flow: PCIe Devices28 minutes
Module 5a: CXL Transaction Flow: Type 3 Devices24 minutes
Module 5b: CXL Transaction Flow: Type 3 Devices39 minutes
Module 6: CXL Transaction Flow: Type 1 Devices23 minutes
Module 7a: CXL Transaction Flow: Type 2 Devices29 minutes
Module 7b: CXL Transaction Flow: Type 2 Devices26 minutes
Module 7c: CXL Transaction Flow: Type 2 Devices21 minutes
Module 8: Transaction Layer Overview43 minutes
Module 9: Link Layer and ARB/MUX Layer Overview28 minutes
Module 10: DVSEC and Component Register Space Overview10 minutes