Comprehensive CXL 2.0 eLearning Course

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Comprehensive CXL 2.0 eLearning Course

Instructor(s): Ravi Budruk
Number of Modules: 71
Subscription Length: 90 days

Course Price
$1,595.00



Compute Express Link (CXL) 2.0 Architecture eLearning Course Info

What's Included?

CXL eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)

Benefits of eLearning:

  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course

You Will Learn:

  • CXL system architectures with Type 1, Type 2 and Type 3 devices
  • CXL transaction protocol for CXL.io and CXL.cache/mem
  • CXL port design constituting Transaction, Link, ARB/MUX and Flex Bus Physical Layers
  • CXL switch architecture (optional)
  • Enumeration and initialization issues with configuration register definitions
  • Power management
  • Reliability, Availability, Serviceability (RAS) and error handling features
  • Considerations to improve protocol performance

Who Should View?

This course is hardware-oriented, but is suitable for both hardware design and software engineers given the course covers CXL initialization topics. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of CXL architecture. The course is also suitable for chip-level and board-level validation engineers.

Course Outline:

  • Module 1: Introduction and Outline
    - Intro to the course, outline and objectives
  • Modules 2a-2c: Features and Architecture Overview
    - These modules are shared with CXL Fundamentals eLearning hence the module titles contain the word Fundamentals
    - Intro to CXL features and device types, description of the CXL Flex Bus Port, example system with CXL Type 2 device, low latency feature and CXL 2.0 vs CXL 1.1
  • Module 3: CXL Port Layer Architecture
    - Port layered architecture, intro to Transaction Layer, Link Layer, ARB/Mux Layer and Physical Layer as well as 64 Byte CXL Flits
  • Module 4: CXL Transaction Flow: PCIe Devices
    - Shows traditional transaction flows of PCIe devices both with and without Private Device Memory (PDM)
  • Modules 5a-5b: CXL Transaction Flow: Type 3 Devices
    - Discusses Type 3 devices as a memory buffer / expander including how it fits in a system's address map, introduces CXL 2.0 with switches and Multi-Logical Devices (MLD)
  • Module 6: CXL Transaction Flow: Type 1 Devices
    - Discusses transaction flows and requirements for Type 1 devices and what can be cached where
  • Modules 7a-7c: CXL Transaction Flow: Type 2 Devices
    - Discusses transaction flows of Type 2 devices and the device characteristics, shows example platform address map with Type 2 CXL devices, discusses host bias versus device bias modes, walks through a transaction flow and CXL's asymmetric coherence protocol
  • Modules 8a-8b: Cache Tutorial
    - Provides a good introduction to cache coherency and the MESI (Modified, Exclusive, Shared, Invalid) protocol
  • Modules 9a-9e: Transaction Layer: CXL.mem Protocol
    - Describes the purpose of the CXL.mem protocol, walks through the different transactions for Master to Subordinate (M2S) and Subordinate to Master (S2M) requests (both reads and writes), provides numerous examples of transaction flows for read and write requests that are cacheable and non-cacheable, host accessing Device Attached Memory (DAM) of a Type 2 and Type 3 device plus speculative read transaction
  • Modules 10a-10i: Transaction Layer: CXL.cache Protocol
    - Describes the purpose of the CXL.cache protocol, walks through the different transactions for Device to Host (D2H) and Host to Device (H2D) requests, responses and data, provides numerous examples of transaction flows for read and write requests, discusses host snooping device cache, device accessing DAM of Type 2 and Type 3 device; host bias vs device bias
  • Module 11: Transaction Layer: CXL.mem and CXL.cache Example
    - Provides examples of a Device accessing DAM of a Type 2 device for Host Bias region and DRSF Hit as well as Device Bias region or DRSF Miss
  • Module 12: Transaction Layer: CXL.io Protocol
    - Describes extensions to the PCIe protocol for CXL: Address Translation Service (ATS) extensions, Deferrable Memory Writes (non-posted writes), Logical Device IDs for devices with Multiple Logical Devices (MLDs), Memory Error Firmware Notifications (MEFN), vendor-defined power management messages, credit and Power Management initialization
  • Module 13: Transaction Layer: Ordering Rules
    - Provides a brief description of the ordering rules in link direction from host to device and device to host
  • Module 14: Link Layer: CXL.io Flit Packing
    - Describes Flits and how traditional PCIe traffic are packed into IO Flits
  • Modules 15a-15b: Link Layer: CXL.cache/mem Flit Packing
    - Walks through detailed descriptions and examples of the three types of Cache/Mem Flits: Protocol Flits, All-Data Flits and Control Flits. Describes cache/mem Flit packing rules with examples
  • Modules 16a-16b: Link Layer: CXL Control Flits
    - Provides descriptions and examples of the different types of Control Flits (e.g., LLCTRL.RETRY, LLCTRL.LLCRD, LLCTRL.IDLE, LLCTRL.INIT), also introduces CXL Cache/Mem flow control protocol
  • Modules 17a-17d: Link Layer: CXL.cache/mem Link Layer Retry (LLR)
    - Detailed coverage of the Link Layer Retry (LLR) protocol including numerous examples, also explains the Local Retry State Machine (LRSM) and Remote Retry State Machine (RRSM)
  • Modules 18a-18c: ARBMux Layer
    - Describes the purpose of the ARM/MUX Layer and then provides detailed explanations of the Virtual Link State Machines (vLSMs) as well as the use of ALMP Flits (both Request ALMPs and Status ALMPs)
  • Modules 19a-19c: Logical Physical Layer
    - Provides detailed descriptions of the Flex Bus Modes of Operation (Normal CXL Mode, Degraded CXL Mode and PCIe Mode), Protocol ID framing, byte striping in 128b/130b mode, Sync Header Bypass Mode (aka Latency Optimized Mode)
  • Modules 20a-20b: Logical Physical Layer: Link Training
    - Detailed coverage of Link Training and Alternate Mode Negotiation, TS1/TS2 vs Modified TS1/TS2, CXL 2.0 vs CXL 1.1 negotiation
  • Modules 21a-21b: Reset
    - Provides descriptions of the different types of reset (Cold, Warm, Hot, Function-Level Reset (FLR) and CXL Reset), also describes device cache management, Global Persistent Flush (GPF) and Hot Plug support
  • Modules 22a-22b: Power Management
    - Covers whole system power management between host and device and the CXL PM VDM transaction communication used to transition through the different phases
  • Module 23: RAS and Error Handling
    - Describes the RAS features provided by PCIe and CXL and which are required vs optional, also explains how errors are reported and differences between DSP vs USP detecting error, CXL MEFN VDM support, CXL Viral Handling also discussed
  • Modules 24a-24d: Enumeration and Manageability
    - Explains both the CXL 1.1 Hierarchy Software Model as well as the 2.0 model, describes how the different software/firmware entities view the system, provides examples of system topologies as the location of different memory mapped structures and how devices decode accesses to those regions; memory interleaving also described
  • Modules 25a-25e: Registers
    - Describes Configuration Space registers for CXL including DVSEC and Component registers, also describes RCRB region and which PCIe capability and extended capability structures are valid for CXL devices, walks through the Component Registers (referred to as MEMBAR0 registers in CXL 1.1 spec), CXL.cache/CXL.mem architectural registers, RAS registers, security policy registers, link capability registers, HDM decoder registers, Ext. security registers, IDE registers, Snoop Filter registers, ARM/MUX registers
  • Modules 26a-26i: Switches
    - Provides a detailed explanation of the three types of CXL Switches (Single Virtual Switch (VCS), Multiple VCS Switch with Single Logical Device (SLD) ports, Multiple VCS Switch with Multi-Logical Device (MLD) ports), shows examples of binding physical ports to virtual ports, describes CXL switch optimization options (static, FM boots before the host(s) or host(s) boot before the FM), sideband signal operation, describes differences between physical PCI-to-PCI Bridges (PPBs) vs Virtual PCI-to-PCI Bridges (vPPBs), Fabric Manager (FM) APIs and CXL switch management

 

Course Modules
ModuleLength
Module 1: Intro 1-1130 minutes
Module 2a: Features and Architecture Overview19 minutes
Module 2b: Features and Architecture Overview16 minutes
Module 2c: Features and Architecture Overview36 minutes
Module 3: CXL Port Layer Architecture39 minutes
Module 4: CXL Transaction Flow: PCIe Devices28 minutes
Module 5a: CXL Transaction Flow: Type 3 Devices24 minutes
Module 5b: CXL Transaction Flow: Type 3 Devices39 minutes
Module 6: CXL Transaction Flow: Type 1 Devices23 minutes
Module 7a: CXL Transaction Flow: Type 2 Devices29 minutes
Module 7b: CXL Transaction Flow: Type 2 Devices26 minutes
Module 7c: CXL Transaction Flow: Type 2 Devices21 minutes
Module 8a: Cache Tutorial30 minutes
Module 8b: Cache Tutorial31 minutes
Module 9a: Transaction Layer: CXL.mem Protocol23 minutes
Module 9b: Transaction Layer: CXL.mem Protocol31 minutes
Module 9c: Transaction Layer: CXL.mem Protocol18 minutes
Module 9d: Transaction Layer: CXL.mem Protocol25 minutes
Module 9e: Transaction Layer: CXL.mem Protocol28 minutes
Module 10a: Transaction Layer: CXL.cache Protocol33 minutes
Module 10b: Transaction Layer: CXL.cache Protocol33 minutes
Module 10c: Transaction Layer: CXL.cache Protocol18 minutes
Module 10d: Transaction Layer: CXL.cache Protocol29 minutes
Module 10e: Transaction Layer: CXL.cache Protocol27 minutes
Module 10f: Transaction Layer: CXL.cache Protocol19 minutes
Module 10g: Transaction Layer: CXL.cache Protocol26 minutes
Module 10h: Transaction Layer: CXL.cache Protocol26 minutes
Module 10i: Transaction Layer: CXL.cache Protocol12 minutes
Module 11: Transaction Layer: CXL.mem and CXL.cache Example34 minutes
Module 12: Transaction Layer: CXL.io Protocol37 minutes
Module 13: Transaction Layer: Ordering Rules16 minutes
Module 14: Link Layer:?CXL.io?Flit Packing31 minutes
Module 15a: Link Layer: CXL.cache/mem Flit Packing52 minutes
Module 15b: Link Layer: CXL.cache/mem Flit Packing34 minutes
Module 16a: Link Layer: CXL Control Flits39 minutes
Module 16b: Link Layer: CXL Control Flits12 minutes
Module 17a: Link Layer: CXL.cache/mem Retry37 minutes
Module 17b: Link Layer: CXL.cache/mem Retry16 minutes
Module 17c: Link Layer: CXL.cache/mem Retry29 minutes
Module 17d: Link Layer: CXL.cache/mem Retry17 minutes
Module 18a: ARBMux Layer19 minutes
Module 18b: ARBMux Layer: vLSMs and ALMP Flits24 minutes
Module 18c: ARBMux Layer: vLSMs and ALMP Flits37 minutes
Module 19a: Logical Physical Layer36 minutes
Module 19b: Logical Physical Layer34 minutes
Module 19c: Logical Physical Layer15 minutes
Module 20a: Logical Physical Layer: Link Training28 minutes
Module 20b: Logical Physical Layer: Link Training38 minutes
Module 21a: Reset31 minutes
Module 21b: Reset19 minutes
Module 22a: Power Management31 minutes
Module 22b: Power Management32 minutes
Module 23: RAS and Error Handling29 minutes
Module 24a: Enumeration and Manageability28 minutes
Module 24b: Enumeration and Manageability32 minutes
Module 24c: Enumeration and Manageability39 minutes
Module 24d: Enumeration and Manageability33 minutes
Module 25a: Registers20 minutes
Module 25b: Registers32 minutes
Module 25c: Registers34 minutes
Module 25d: Registers22 minutes
Module 25e: Registers34 minutes
Module 26a: Switches17 minutes
Module 26b: Switches33 minutes
Module 26c: Switches25 minutes
Module 26d: Switches34 minutes
Module 26e: Switches22 minutes
Module 26f: Switches27 minutes
Module 26g: Switches26 minutes
Module 26h: Switches23 minutes
Module 26i: Switches33 minutes