Comprehensive PCIe 5.0 eLearning Course

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Comprehensive PCIe 5.0 eLearning Course
Advanced PCIe eLearning Course
Fundamentals of PCI Express eLearning Course
PIPE 6.0 - PHY Interface for PCI Express and more
PCIe 4.0 Update
Comprehensive PCI Express 3.1 eLearning Course
PCI Express Power Management eLearning Course
PCI Express Config Space and Transaction Routing eLearning Course
PCI Express Physical Layer and Link Initialization and Training eLearning Course
PCI Express Hot Plug and Resets eLearning Course
PCI Express 2.x and 3.x ECNs eLearning Course
PCI Express Interrupt Handling eLearning Course
PCI Express Error Handling eLearning Course
Intro to PCI Express IO Virtualization eLearning Course
Mobile PCI Express (M-PCIe) eLearning Course
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xHCI eLearning Course
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Comprehensive PCIe 5.0 eLearning Course

Instructor(s): Mike Jackson
Number of Modules: 42
Subscription Length: 90 days

Pre-Order Price: $1,395.00
Regular Price: $1595.00
(release date: March 2021)
Bundle Price (Course & Arbor)
$1,795.00
(more info on Arbor)



Comprehensive PCI Express 5.0 (w/ PIPE) eLearning Course Info

What's Included?

PCI Express 5.0 eLearning modules and PIPE 6.0 eLearning Modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)
PCI Express eBook
(yours to keep, does not expire)

Benefits of eLearning:

  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course

You Will Learn:

  • PCI Express features and capabilities
  • The definition and responsibilities of each of the layers in the interface
  • How hardware-based automatic error detection and correction mechanism works
  • The various additional levels of error detection and reporting
  • The details of the packet-based protocol used by PCIe
  • The address space and packet-routing methods used
  • How the various power management techniques work
  • Configuration register details that provide control and status visibility to software
  • The purpose of equalization and how it is done in PCIe 3.0 and later


If you are going to take one course on PCI Express, this should be it. MindShare's PCIe eLearning course is an exhaustive tutorial on PCIe from the electrical PHY all the way up to software. It starts with a high-level view of the design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.

Who Should View?

This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers.

PCIe 5.0 Module Descriptions:

  • Module 1: PCIe Background Info
    - Coverage of basics from PCI that carry forward into PCI Express
  • Module 2a: PCIe Overview
    - High level overview of PCIe; Component types, device layers, transaction types, etc.
  • Module 2b: PCIe Overview
    - High level overview of PCIe; Component types, device layers, transaction types, etc.
  • Module 2c: PCIe Overview
    - High level overview of PCIe; Component types, device layers, transaction types, etc.
  • Module 3: Configuration Space Overview
    - Basics of config space registers and accessing config space and includes an intro to the Arbor software tool
  • Module 4: Address Space and Transaction Routing
    - Covers the behavior and programming of BARs and Base and Limit registers as well as routing methods in a PCIe system
  • Module 5a: TLP Elements
    - Discusses all TLP types and the header fields for each (memory, IO, config, messages, etc.)
  • Module 5b: TLP Elements
    - Discusses all TLP types and the header fields for each (memory, IO, config, messages, etc.)
  • Module 5c: TLP Elements
    - Discusses all TLP types and the header fields for each (memory, IO, config, messages, etc.)
  • Module 6: Quality of Service
    - Traffic classes, virtual channels, and arbitration schemes
  • Module 7a: Flow Control
    - Protocol of flow control including credit values and frequency of transmission
  • Module 7b: Flow Control
    - Protocol of flow control including credit values and frequency of transmission
  • Module 8: Transaction Ordering
    - Ordering rules
  • Module 9: DLLP Elements
    - Coverage of DLLP types and their contents
  • Module 10a: DLLP Elements and Ack/Nak Protocol
    - Coverage of Ack/Nak state-machine and example scenarios
  • Module 10b: DLLP Elements and Ack/Nak Protocol
    - Coverage of Ack/Nak state-machine and example scenarios
  • Module 11a: Physical Layer: Logical (8b/10b)
    - Transmit side: Byte striping, scrambling, 8b/10b, SerDes
  • Module 11b: Physical Layer: Logical (8b/10b)
    - Receive (Rx) side: CDR, Elastic Buffer, SKP ordered-sets, Lane-to-lane deskew, 8b/10b decoding
  • Module 12a: Physical Layer: Logical (128b/130b)
    - Byte striping, scrambling, 128/130b, packet encapsulation
  • Module 12b: Physical Layer: Logical (128b/130b)
    - Byte striping, scrambling, 128/130b, packet encapsulation
  • Module 13: Physical Layer: Electrical
    - High-speed signaling, differential signals, ISI, de-emphasis, equalization, eye diagrams
  • Module 14a: Link Initialization and Training
    - LTSSM(Detect, Polling, Configuration, Recovery), link and lane numbering, speed change
  • Module 14b: Link Initialization and Training
    - Equalization procedure, dynamic link width changes, loopback, etc.
  • Module 15: Interrupts
    - Interrupt messages, MSI, MSI-X
  • Module 16a: Error Detection and Handling
    - Correctable, Non-Fatal, and Fatal errors and how they're reported and handled (PCI-compatible, baseline, and advanced error reporting)
  • Module 16b: Error Detection and Handling
    - Correctable, Non-Fatal, and Fatal errors and how they're reported and handled (PCI-compatible, baseline, and advanced error reporting)
  • Module 17: Power Management
    - Device power states (D0, D1, D2, D3), link power states (L0, L0x, L1, L2, L2/L3 Ready, L3), Active State Power Management (ASPM), Software power management, power management events (PME), Dynamic Power Allocation (DPA), Optimized Buffer Flush Fill (OBFF), Latency Tolerance Reporting (LTR)
  • Module 18: System Resets
    - Hot, Warm, Cold and Function-Level resets
  • Module 19: Retimers
    - Intro to Retimers, definition of link segments and pseudo-ports, forwarding mode and execution mode, what retimers can modify, handling electrical idle, handling training of links (and link segments) with a focus on Tx equalization
  • Module 20: Lane Margining
    - Intro to lane margining, time margining concept, voltage margining concept, Lane Margining Extended Capability structure, initiating margining commands, performing lane margining on a retimer (Control SKP ordered sets)
  • Module 21: Flattening Portal Bridges (FPB)
    - Static allocation limits, removing the designated bus number within a switch, dynamic allocation limits, FPB Routing ID vector and FPB Memory routing vector, solution for hot plug environments
  • Module 22: Hierarchy ID, DVSEC, Enhanced Allocation and Emergency Power Reduction
    - Intro to Hierarchy ID messages and capability structure, intro to Designated Vendor-Specific (DVSEC) feature, intro to Enhanced Allocation feature (for embedded environments), intro to Emergency Power Reduction State
  • Module 23: System Firmware Intermediary (SFI)
    - Choosing to notify firmware or the OS
  • Module 24: Downstream Port Containment (DPC and eDPC)
    - Handling of events that should be isolated
  • Module 25: Multi-Casting
    - What it is and how it works
  • Module 26: Protocol Multiplexing
    - An optional feature allowing other protocols to simultaneously share the PCIe link
  • Module 27: TLP Processing Hints and Steering Tags
    - Describes the TLP fields involved and how the Root Complex interprets them
  • Module 28: Alternative Routing-ID Interpretation (ARI)
    - Describes the purpose of ARI and affects it may have in a system
  • Module 29: Atomic Operations
    - Covers the different atomic ops supported in PCIe
  • Module 30: Resizable BARs
    - Provides background for the purpose of resizable BARs and how they
  • Module 31: L1 Substates
    - Goes through this important addition to link power management
  • Module 32: Lightweight Notification
    - Provides context of why this can be useful for caching data in a PCIe function and how it works
  • Module 33: Process Address Space ID (PASID)
    - Provides a brief into to the main uses of PASID with IOMMUs
  • Module 34: Precision Time Measurement (PTM)
    - Goes over the mechanism to share a common time domain with very tight timing requirements in PCIe systems
  • Module 35: Device Readiness Status (DRS) and Function Readiness Status (FRS)
    - Talks about the purpose of this feature
  • Module 36: Hot Plug
    - Discusses the hot plug features in PCIe
  • Module 37: Power Budgeting
    - Provides insight in how a function can advertise its power requirements in a standard way

PIPE 6.0 Module Descriptions:

  • Module 1: Introduction
    - Intro to PIPE, Original PIPE vs SerDes PIPE, PCLK options, data throttling, Message Bus intro, interface types (legacy vs low pint count, LPC), registers in MAC and PHY, combining PIPEs for multi-lane link
  • Module 2a: PHY/MAC Interface (Intro)
    - Interface support options, Short-Reach (SR) applications, terminology of signal names in spec
  • Module 2b: PHY/MAC Interface (Common Signals)
    - External signals, command signals, command interface inputs to PHY, SRIS motivation, power states, receiver detection, command interface status outputs, PHY status signals (inputs and output), data signal, block synchronization, original PIPE block diagrams
  • Module 2c: PHY/MAC Interface (Original and SerDes specific signals)
    - SerDes signals, original PIPE signals, Message Bus, Message Bus commands, command formats, Message Bus rules
  • Module 3: PHY Registers
    - PHY register list, register definitions, register groups, intro to equalization, PCIe EQ starting parameters, delivering Tx FS/LF values, speed change example, getting local coefficients example, updating PHY Tx values
  • Module 4: MAC Registers
    - Elastic buffer registers, signal integrity, PHY recalibration, link equalization evaluation, Gen5 Tx parameters, local preset values, Gen3 and Gen4 Tx parameters
  • Module 5: PIPE Operational Behavior: PCIe Mode
    - Key features, voltage margining, Tx options (e.g. low voltage), de-emphasis intro and setting de-emphasis value, Inter-Symbol Interference (ISI)
  • Module 6a: Equalization Process
    - Equalization commonalities across protocols, 3-tap equalizer, preset encodings, effect of Tx equalization, location of EQ circuitry and logic, initializing preset values, fetching PHY Tx values for preset(s), Tx equalizer values, relationship between coefficients and FS, MAC tells PHY what coefficients to use, MAC applies coefficients
  • Module 6b: Equalization Process
    - Equalization phase summary, EQ phase 1 step through, EQ phase 2 step through, accepting vs rejecting coefficients, EQ phase 3 step through, Tx EQ finishing, Rx equalization
  • Module 7: PCIe Lane Margining
    - Lane margining background, time margining concept, voltage margining concept, SW in control of margining, related configuration registers for PCIe, location of config space, margining register encodings for PCIe, determining what's an error, step time margin command, step voltage margin command, step margin command response, dependent vs independent samplers, affected PHY registers, margining a retimer, receiver numbers, affected MAC registers
  • Module 8: PCIe Elastic Buffer
    - Purpose of elastic buffer, nominal half-full buffer, adding / removing SKPs (skips), nominal empty buffer, PHY elastic buffer registers
  • Module 9: PCIe Power States
    - Intro to power states, timing diagrams for L0 to L0s entry and exit, timing diagram for L0 to L1 entry and exit, L1 substates, receiving electrical idle
  • Module 10: PIPE Operational Behavior: USB Mode
    - Key features, USB power states, low frequency periodic signaling (LFPS), variants of LFPS, receiver detection, USB equalization, forcing compliance patterns
  • Module 11: PIPE Operational Behavior: SATA Mode
    - Key features, Out of Band (OOB) signaling, OOB and alignment, SATA speed negotiation, SATA power states
Course Modules
Coming Soon!