Core PCIe eLearning Course

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Core PCIe eLearning Course

Instructor(s): Mike Jackson
Number of Modules: 41
Subscription Length: 90 days

Course Price
$995.00
Bundle Price (Course & Arbor)
$1,395.00
(more info on Arbor)



Core PCI Express eLearning Course Info

What's Included?

Core PCI Express eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)
PCI Express eBook
(yours to keep, does not expire)

Benefits of eLearning:

  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course

You Will Learn:

  • PCI Express features and capabilities
  • The definition and responsibilities of each of the layers in the interface
  • How hardware-based automatic error detection and correction mechanism works
  • The various additional levels of error detection and reporting
  • The details of the packet-based protocol used by PCIe
  • The address space and packet-routing methods used
  • How the various power management techniques work
  • Configuration register details that provide control and status visibility to software
  • The purpose of equalization and how it is done in PCIe 3.0 and later


If you are going to take one course on PCI Express, this should be it. MindShare's PCIe eLearning course is an exhaustive tutorial on PCIe from the electrical PHY all the way up to software. It starts with a high-level view of the design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.

Who Should View?

This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers.

PCIe 5.0 Module Descriptions:

  • Module 1: PCIe Background Info
    - Coverage of basics from PCI that carry forward into PCI Express
  • Module 2: PCIe Overview
    - High level overview of PCIe; Component types, device layers, transaction types, etc.
  • Module 3: Configuration Space Overview
    - Basics of config space registers and accessing config space and includes an intro to the Arbor software tool
  • Module 4: Address Space and Transaction Routing
    - Covers the behavior and programming of BARs and Base and Limit registers as well as routing methods in a PCIe system
  • Module 5: TLP Elements
    - Discusses all TLP types and the header fields for each (memory, IO, config, messages, etc.)
  • Module 6: Quality of Service
    - Traffic classes, virtual channels, and arbitration schemes
  • Module 7: Flow Control
    - Protocol of flow control including credit values and frequency of transmission
  • Module 8: Transaction Ordering
    - Ordering rules
  • Module 9: DLLP Elements
    - Coverage of DLLP types and their contents
  • Module 10: DLLP Elements and Ack/Nak Protocol
    - Coverage of Ack/Nak state-machine and example scenarios
  • Module 11: Physical Layer: Logical (8b/10b)
    - Receive (Rx) side: CDR, Elastic Buffer, SKP ordered-sets, Lane-to-lane deskew, 8b/10b decoding
  • Module 12: Physical Layer: Logical (128b/130b)
    - Byte striping, scrambling, 128/130b, packet encapsulation
  • Module 13: Physical Layer: Electrical
    - High-speed signaling, differential signals, ISI, de-emphasis, equalization, eye diagrams
  • Module 14: Link Initialization and Training
    - LTSSM(Detect, Polling, Configuration, Recovery), link and lane numbering, speed change
  • Module 15: Interrupts
    - Interrupt messages, MSI, MSI-X
  • Module 16: Error Detection and Handling
    - Correctable, Non-Fatal, and Fatal errors and how they're reported and handled (PCI-compatible, baseline, and advanced error reporting)
  • Module 17: Power Management
    - Device power states (D0, D1, D2, D3), link power states (L0, L0x, L1, L2, L2/L3 Ready, L3), Active State Power Management (ASPM), Software power management, power management events (PME), Dynamic Power Allocation (DPA), Optimized Buffer Flush Fill (OBFF), Latency Tolerance Reporting (LTR)
  • Module 18: System Resets
    - Hot, Warm, Cold and Function-Level resets
Course Modules
ModuleLength
Module 1a: Introduction and Background36 minutes
Module 1b: Introduction and Background 30 minutes
Module 2a: Architecture Overview 33 minutes
Module 2b: Architecture Overview 33 minutes
Module 2c: Architecture Overview 28 minutes
Module 3: Configuration Space Overview 61 minutes
Module 4: Address Space and Transaction Routing 49 minutes
Module 5a: TLP Elements 28 minutes
Module 5b: TLP Elements 35 minutes
Module 5c: TLP Elements 37 minutes
Module 6: Quality of Service 41 minutes
Module 7a: Flow Control 32 minutes
Module 7b: Flow Control 20 minutes
Module 8: Transaction Ordering 16 minutes
Module 9: DLLP Elements 10 minutes
Module 10a: Ack/Nak Protocol 32 minutes
Module 10b: Ack/Nak Protocol 28 minutes
Module 11a: Physical Layer: Logical (8b/10b) 33 minutes
Module 11b: Physical Layer: Logical (8b/10b) 41 minutes
Module 12a: Physical Layer: Logical (128b/130b) 28 minutes
Module 12b: Physical Layer: Logical (128b/130b) 27 minutes
Module 12c: Physical Layer: Logical (128b/130b) 22 minutes
Module 12d: Physical Layer: Logical (128b/130b) 35 minutes
Module 12e: Physical Layer: Logical (128b/130b) 26 minutes
Module 13a: Physical Layer: Electrical 41 minutes
Module 13b: Physical Layer: Electrical 33 minutes
Module 13c: Physical Layer: Electrical 38 minutes
Module 14a: Link Initialization and Training (LTSSM) 23 minutes
Module 14b: Link Initialization and Training (LTSSM) 29 minutes
Module 14c: Link Initialization and Training (LTSSM) 29 minutes
Module 14d: Link Initialization and Training (LTSSM) 31 minutes
Module 14e: Link Initialization and Training (LTSSM) 33 minutes
Module 14f: Link Initialization and Training (LTSSM) 49 minutes
Module 14g: Link Initialization and Training (LTSSM) 31 minutes
Module 14h: Link Initialization and Training (LTSSM) 15 minutes
Module 15: Interrupts 46 minutes
Module 16a: Error Detection and Reporting 38 minutes
Module 16b: Error Detection and Reporting 45 minutes
Module 17a: Power Management 28 minutes
Module 17b: Power Management 49 minutes
Module 18: System Resets 13 minutes