Fundamentals of PCI Express eLearning Course

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Fundamentals of PCI Express eLearning Course

Instructor(s): Mike Jackson
Number of Modules: 13
Subscription Length: 90 days

Course Price
Bundle Price (Course & Arbor)
(more info on Arbor)
Bundle Price (CXL & PCIe Fundamentals)

Fundamentals of PCI Express eLearning Course Info

UPDATED for PCIe 5.0

What's Included?

Fundamentals of PCIe eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)

Benefits of eLearning:

  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course

You Will Learn:

  • Short background of PCI concepts important to PCIe
  • Motivation for PCIe serial model
  • Software view of the topology
  • Definition and responsibilities of each layer in the PCIe interface
  • PCIe transaction types and definitions
  • The routing method used for each request and completion
  • Roles of the Flow Control and ACK / NAK features
  • Purpose and behavior of the logical blocks within the Physical Layer
  • Error types and the associated levels of severity

Who Should View?

This course provides a great overview of the basics of the PCI Express technology and is for individuals who need to know the fundamentals of PCI Express but not the low-level implementation or validation details. This course was designed with FAEs and managers in mind but is also a great jump-start for design/validation/verification engineers wanting to learn this IO bus. If you are looking for a course that covers more of the low-level details and features, please check out our Comprehensive PCI Express eLearning Course.

Course Outline:

  • Module 1: Introduction and Background
    - Describes the pieces of PCI relevant for PCIe as well as traditional traffic types and a typical transaction between an IO device and its device driver
  • Module 2a: PCIe Architecture Overview
    - Describes: Links, Lanes, Throughput, PCIe Topologies, Root Complexes, Endpoints, Switches, and example topologies
  • Module 2b: PCIe Architecture Overview
    - Provides overview of the PCIe protocol layers, Transaction Layer Packet (TLP) types and format, Quality of Service (QoS) and transaction ordering rules
  • Module 2c: PCIe Architecture Overview
    - Provides an overview of flow control, Data Link Layer Packets (DLLPs), Ack/Nak protocol, framing of packets at Physical Layer, ordered set formats, and a review of electrical Physical Layer
  • Module 3: Configuration Space
    - Provides an overview of legacy configuration space access mechanism as well as Enhanced Configuration Access Mechanism (ECAM), shows type 1 vs type 0 configuration headers, discusses legacy capability structures as well as extended capability structures and the linked list
  • Module 4: Address Space Allocation
    - Discusses prefetchable vs non-prefetchable MMIO, Base Address Registers (BARs) and how they request size and type of address space and how software allocates space to a BAR, how Base and Limit registers (address windows) are programmed by software and how a bridge interprets those values
  • Module 5: Interrupt Support
    - Brief introduction to legacy interrupt emulation as well as how Message Signaled Interrupts (MSIs) work in PCIe
  • Module 6: Error Detection and Reporting
    - Defines classes of errors: Correctable, Non-Fatal and Fatal as well as covers error reporting behaviors: PCI-compatible, baseline and Advanced Error Reporting (AER)
  • Module 7: Power Management
    - Introduces power states of a device (D0, D1, D2 and D3), power states of a link (L0, L0s, L1.0, L1.1, L1.2, L2, L3), discusses the relationship between device power states and link power states
  • Module 8: Physical Layer - Logical
    - Gives an introdcution to the logical portion of the Physical Layer for both 8b/10b speeds (2.5GT/s and 5.0GT/s) as well as 128b/130b speeds (8.0GT/s, 16.0GT/s and 32.0GT/s)
  • Module 9: Physical Layer - Electrical
    - Introduces differential signaling, de-emphasis, Tx equalization and the 3-tap equalizer
  • Module 10: Link Initialization and Training
    - Shows Training Sequence 1 and 2 (TS1 and TS2) ordered sets and a simplified view of the Link Training Status State Machine (LTSSM)
  • Module 11: PCIe 4.0 and 5.0 Updates
    - Discusses the purpose and behavior of Retimers, lane margining (both time margining and voltage margining) and a brief introduction to PCIe 5.0 updates
Course Modules
Module 1: Introduction and Background40 minutes
Module 2a: PCIe Architecture Overview27 minutes
Module 2b: PCIe Architecture Overview36 minutes
Module 2c: PCIe Architecture Overview26 minutes
Module 3: Configuration Space22 minutes
Module 4: Address Space Allocation20 minutes
Module 5: Interrupt Support17 minutes
Module 6: Error Detection and Reporting14 minutes
Module 7: Power Management17 minutes
Module 8: Physical Layer - Logical24 minutes
Module 9: Physical Layer - Electrical13 minutes
Module 10: Link Initialization and Training18 minutes
Module 11: PCIe 4.0 and 5.0 Updates15 minutes