- Module 1: Introduction and Outline
- Intro to the course, outline and objectives
- Modules 2a-2b: Background
- Introduces I3C and the motivation for it; reviews I2C protocol and points out limitations of I2C
- Module 3a-3b: Bus Topology
- Describes I3C controllers (both primary and secondary), I3C targets (both single-function and composite targets) and describes compatibility of I2C devices on an I3C bus (Fast Mode (FM), Fast Mode Plus (FM+) and implications of I2C spike filter)
- Module 4a-4b: Device Capability Discovery
- Summarizes required and optional features of I3C (e.g. multi-lane SDA, high data rates (HDR-DDR, HDR-BT, HDR-TSP and HDR-TSL), better power conservation, improved addressing, arbitrated events), introduces I3C private messages as well as Common Command Code (CCC) messages, describes how software can retrieve the capabilites of targets on the I3C bus
- Modules 5a-5d: Bus Communication Basics
- Covers big picture behavior of I3C devices and messages, communication flows (I2C as well as SDR and HDR), the starting and stopping of I3C transactions, dynamic driver switching (open drain vs push-pull), bus conditions and activity states and arbitration on the I3C bus
- Module 6a-6c: SDR Message Details
- Finishes the discussion of SDR private read/write messages, also covers more details on CCC messages (broadcast vs direct CCCs, the different CCC message groups and shows some examples of CCC message sequences)
- Modules 7a-7b: Bus Initialization and DAA
- Describes some of the primary I3C bus initialization tasks, including Dynamic Address Assignment (DAA); shows details for SETAASA, RSTDAA, ENTDAA, SETNEWDA and SETDASA CCC messages; walks through the sequence of events to assign addresses to targets on the bus
- Modules 8: Hot-Join Mechanism
- Walks through what Hot-Join is as well as its motivation and behavior
- Modules 9: In-Band Interrupt (IBI)
- Provides some motivations for in-band interrupts; shows how a target advertises whether it is IBI capable and if an interrupt is pending; also discusses how IBIs are enabled, prioritized and deferred; then walks through an example of a target generating an IBI
- Modules 10a-10b: Secondary Controllers
- Covers primary and secondary controller variants, I3C active controller rules, tracking target and address group info, checking secondary controller capabilities, and how the handoff is initiated and executed
- Module 11: HDR-DDR Protocol
- Discusses the optional High Data Rate mode that uses Double Data Rate clocking (HDR-DDR); the behavior of HDR-DDR signaling and format of reads and writes; also describes how I2C devices react to this signaling
- Module 12a-12b: HDR-BT Protocol
- Provides background as the types of devices that can benefit from High Data Rate Bult Transfer (HDR-BT) Mode; walks through the format of data transfers as well as CRC protection, etc.
- Module 13: Multi-Lane Data Transfers
- Describes how I3C bus transfers can be conducted with a multi-lane (ML) SDA interface; striping of data across the lanes; three encoding schemes (Coding 0, Coding 3 and Coding 7); checking connectivity, choosing encoding scheme
- Module 14: Host Controller Overview
- Covers I3C HCI motivations and scope, HC connection via PCIe, two programming interfaces (Programmed IO (PIO) and Direct Memory Access (DMA)), describes both PCI config space registers as well as MMIO registers
- Modules 15a-15c: HCI PIO and DMA Operations
- Describes the differences between PIO and DMA modes of operation; shows different queues that are involved for each, buffer management, enqueue and dequeue pointers, command and transfer descriptors
