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IO Virtualization for Intel Platforms eLearning Course
Instructor(s): Joe Winkles
Number of Modules: 29
Subscription Length: 90 days
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Course Price
$695.00 |
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IO Virtualization on Intel Platforms
What's Included?
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IOV Intel eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
Who Should View?
This course is meant for anyone wanting a good understanding of virtualization for IO devices which includes the concepts of what needs to be done, the problems that need to be solved and the technologies (both standard and non-standard) to help overcome the challenges. This course provides a significant amount of background information to help explain the normal operating environment in order to understand how it should be virtualized. Both hardware and software engineers will benefit from this course.
Course Outline:
- Module 1: eLearning Intro and Course Outline
- Intro to the eLearning course and review of the course outline
- Module 2a: Introduction to Virtualization
- Defining virtualization, Type 1 vs Type 2 hypervisor, trap and emulate, PCI config space emulation, real vs emulated systems, emulate and trapping MMIO
- Module 2b: Introduction to Virtualization
- Complexities of virtualization, ring deprivileging, paravirtualization, binary translation, intro to Intel VT-x, VMX Root Mode (host mode) and VMX Non-Root Mode (guest mode), VMCS, Intel VT-x usage example
- Module 3a: Background: x86 Paging, TLBs and Virtualization
- Discuss paging concepts, x86 paging implementation, 4KB vs 2MB vs 1GB pages
- Module 3b: Background: x86 Paging, TLBs and Virtualization
- Purpose of Translation Lookaside Buffers (TLBs), sizing of TLBs, context switches, global pages, Process Context IDs (PCIDs), paging structure caches, software maintenance of TLBs
- Module 3c: Background: x86 Paging, TLBs and Virtualization
- Virtualization affect on paging, guest virtual address (gVA) vs guest physical address (gPA) vs host physical address (hPA), shadow page tables, extended (nested) page tables, Virtual Process IDs (VPIDs)
- Module 4: Background: x86 Address Spaces and "Typical" SW / HW Interactions
- Intro to memory address space vs IO address space vs PCI config space, Programmed IO (PIO) vs Direct Memory Access (DMA) vs Peer-to-Peer (P2P), example of typical interaction between a driver (SW) and its device (HW)
- Module 5a: Virtualization and IO Devices
- Explaining the challenges of IO virtualization, example of emulation approach, example of pararvirtualization approach
- Module 5b: Virtualization and IO Devices
- Example of PCI passthrough approach, discuss how Single-Root IO Virtualization (SRIOV) fits, performance is important for runtime operations, address-related issues, interrupt-related issues, DMA problem, IOMMU to the rescue, IOMMU also for security
- Module 6a: PCIe: Address Translation Services (ATS)
- IOMMU translating DMA operations on-the-fly takes time, IOTLB helps, device TLBs aka Address Translation Caches (ATCs), populating an ATC, translation requests, translation completions, configuration structure
- Module 6b: PCIe: Address Translation Services (ATS)
- Transactions needed to support TLBs on IO devices (known as ATCs), invalidate requests, invalidate completions, unsuccessful translation requests
- Module 7: PCIe: Page Request Interface (PRI)
- Targeting a "not present" page, one solution: paravirtualized device driver, another solution: Page Request Services, page request example, page request messages, PRG Response Messages, configuration structure
- Module 8: PCIe: Access Control Services (ACS)
- What is ACS, seven features: Peer-to-Peer Request Redirect, Peer-to-Peer Completion Redirect, Upstream Forwarding, Peer-to-Peer Egress Control, Direct Translated Peer-to-Peer, Translation Blocking, Source Validation
- Module 9a: PCIe: Single-Root IOV (SRIOV)
- Goals of IOV solution, PCIe IOV terminology, physical function (PF), virtual function (VF), example interface per BDF, config space per BDF, config structure, SRIOV config registers, Number of VFs, how many VFs possible
- Module 9b: PCIe: Single-Root IOV (SRIOV)
- How many functions, BDFs (Requester IDs) of VFs, Vendor ID (VID) and Device ID (DID) of VFs, trapping config space accesses, look at actual system with SRIOV in use
- Module 9c: PCIe: Single-Root IOV (SRIOV)
- VF Base Address Registers (BARs), VF BAR allocation, SRIOV page sizes, migration, error handling, interrupts, power management, VFs and reset
- Module 10a: Intel VT-d: Legacy Mode (No PASIDs)
- IOMMU functionality, DMA Remapping (DMAR) Engines, domains, hypervisor table maintenance, DMAR implementation examples, IOMMU behavior (legacy mode), Requester ID (BDF) lookup, Root Table, Root Entry format, Context Table, Context Entry format
- Module 10b: Intel VT-d: Legacy Mode (No PASIDs)
- Address translation process, 2nd Stage paging structures (4KB, 2MB, 1GB pages), 2nd Stage page table entry format, IOMMU caches and IOTLB, software maintenance of IO caches and IOTLBs, invalidation commands, DMA draining, address translation faults, non-recoverable faults vs recoverable faults, reporting non-recoverable faults, primary fault logging, advanced fault logging
- Module 11: Shared Virtual Memory (SVM)
- General purpose GPUs and accelerators, using virtual addresses at IO devices, SVM example (VA -> PA), SVM issues to resolve
- Module 12: PCIe: Process Address Space ID (PASID)
- PASID goal, use of prefixes in PCIe, PASID prefix, execute and privileged request bits, config structure, adding translation support
- Module 13a: Intel VT-d: Scalable Mode (PASID Support)
- Each process (application) has its own VA space, using VA at IO devices, address translation in Scalable Mode, BDF lookup, Root Entry format, Context Entry format, PASID lookup, PASID Directory Entry format, 1st Stage page table entry format
- Module 13b: Intel VT-d: Scalable Mode (PASID Support)
- SVM within a Guest?, nested address translation, 1st and 2nd stage translation, when to do 1st vs 2nd vs both, handling faults
- Module 14: Intel Scalable IO Virtualization
- Introduction, Scalable IOV vs SRIOV, Assignable Device Interface (ADI), fast-path vs slow-path, virtual device (function) composition, translation / protection problem, PASIDs to the rescue, ADI MMIO space, ADI interrupts, config structure (DVSEC), benefits of Scalable IOV
- Module 15a: Background: x86 Interrupts and Controllers
- Legacy interrupt delivery, INTR on processor, 8259A PIC, APICs introduced, Local APIC and IO APIC, Local APIC per logical processor
- Module 15b: Background: x86 Interrupts and Controllers
- Local APIC register set, APIC interrupt delivery example, queued interrupts, nested interrupts, End of Interrupt (EOI), other interrupt controllers, where to deliver interrupt, Local APIC identifiers, physical destination mode vs logical destination mode, flat logical vs cluster logical, redirectable interrupts, informed redirection, Inter-Processor Interrupts (IPIs)
- Module 15c: Background: x86 Interrupts and Controllers
- Message Signaled Interrupts (MSIs) introduced, vector and delivery info in MSI memory write, MSI address and data encoding, MSI config space structure, MSI example
- Module 16: Background: x86 Interrupts and Virtualization (Intel VT-x)
- Real system vs fake system, virtual interrupts, Intel VT-x event (interrupt) injection, virtualizing an APIC, Intel VT-x vAPIC support, vAPIC page, vINTR concept
- Module 17a: Intel VT-d: Interrupt Remapping
- What is interrupt remapping, purpose, MSI remappable format, Interrupt Remapping Table (IRT), IRT Entry format (direct remapping), interrupt remapping example
- Module 17b: Intel VT-d: Interrupt Remapping
- Interrupt example with emulation, interrupt example with passthrough device, make DMAR and CPU smarter, IRT Entry format (posted interrupts), Posted Interrupt Descriptor (PID), interrupt posting example, when to send notification interrupt, CPU behavior on posted interrupt, another example when target guest is not running, another example with urgent interrupt, interrupt remapping faults, reporting of faults
 | Course Modules |
| Module | Length | | Module 1: eLearning Intro and Course Outline | 16 minutes | | Module 2a: Introduction to Virtualization | 39 minutes | | Module 2b: Introduction to Virtualization | 34 minutes | | Module 3a: Background: x86 Paging, TLBs and Virtualization | 27 minutes | | Module 3b: Background: x86 Paging, TLBs and Virtualization | 23 minutes | | Module 3c: Background: x86 Paging, TLBs and Virtualization | 27 minutes | | Module 4: Background: x86 Address Spaces and "Typical" SW / HW Interactions | 37 minutes | | Module 5a: Virtualization and IO Devices | 29 minutes | | Module 5b: Virtualization and IO Devices | 32 minutes | | Module 6a: PCIe: Address Translation Services (ATS) | 36 minutes | | Module 6b: PCIe: Address Translation Services (ATS) | 24 minutes | | Module 7: PCIe: Page Request Interface (PRI) | 27 minutes | | Module 8: PCIe: Access Control Services (ACS) | 29 minutes | | Module 9a: PCIe: Single-Root IOV (SRIOV) | 38 minutes | | Module 9b: PCIe: Single-Root IOV (SRIOV) | 25 minutes | | Module 9c: PCIe: Single-Root IOV (SRIOV) | 30 minutes | | Module 10a: Intel VT-d: Legacy Mode (No PASIDs) | 47 minutes | | Module 10b: Intel VT-d: Legacy Mode (No PASIDs) | 35 minutes | | Module 11: Shared Virtual Memory (SVM) | 20 minutes | | Module 12: PCIe: Process Address Space ID (PASID) | 16 minutes | | Module 13a: Intel VT-d: Scalable Mode (PASID Support) | 28 minutes | | Module 13b: Intel VT-d: Scalable Mode (PASID Support) | 25 minutes | | Module 14: Intel Scalable IO Virtualization | 40 minutes | | Module 15a: Background: x86 Interrupts and Controllers | 28 minutes | | Module 15b: Background: x86 Interrupts and Controllers | 51 minutes | | Module 15c: Background: x86 Interrupts and Controllers | 15 minutes | | Module 16: Background: x86 Interrupts and Virtualization (Intel VT-x) | 21 minutes | | Module 17a: Intel VT-d: Interrupt Remapping | 24 minutes | | Module 17b: Intel VT-d: Interrupt Remapping | 61 minutes | | |
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