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Modern DRAM (DDR5 / DDR4 / LPDDR5 / LPDDR4) eLearning Course
Instructor(s): John Swindle
Number of Modules: 86
Subscription Length: 90 days
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Course Price
$1,595.00 |
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DRAM eLearning Course Info
What's Included?
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DRAM eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
You Will Learn:
- Where JEDEC expects DRAM to appear in a system
- How a DRAM cell is addressed by the controller
- Difference between Banks, Bank Groups and Ranks
- Why the DRAM controller is so complicated
- Activation, Precharge and Refresh
- DDR4 pin definitions
- DDR4 bank state diagram
- DDR4 timing waveforms
- Prefetch Width
- Types of DIMMs
- Fly-By Routing
- PC and LP DRAM device architectures and features including DDR5 and LPDDR5
- DDR5/LPDDR4/LPDDR5 pin definitions
- DDR5/LPDDR4/LPDDR5 bank state diagrams
- DDR5/LPDDR4/LPDDR5 timing waveforms
- DDR5 DIMM PMIC
- Intro to NVDIMM
- Newer forms of Refresh
- POD and LVSTL signaling
- Clock throttling and dynamic voltage changes
- On-Die Termination (ODT)
- JEDEC Initialization and Mode Registers
- Calibration and training, including
- Vref training
- Read and Write calibration
- Write Leveling
- Sources of errors and JEDEC features for handling errors
- Test philosophy and JEDEC features to assist with testing
Who Should View?
This course is hardware-centric and also describes initialization and training of DRAM devices and controllers. It is suitable for hardware engineers and software/firmware engineers will also benefit. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers. This course introduces current DRAM technologies, concentrating on DDR4 as a baseline to teach concepts that are common to all DRAMs. The course then continues to cover in detail all new features of DDR5, DDR4, LPDDR5, and LPDDR4.
Course Outline:
- Module 1: Introduction and Outline
- Intro to the course, outline and objectives
- Module 2: System Architecture
- Shows where DRAM fits in traditional and non-traditional computer systems
- Module 3: Intro to DRAM
- Discusses the history of DRAM and the pros / cons of DRAM vs SRAM, also describes DRAM cell architecture
- Module 4: DRAM Device Architecture
- Shows how the evolution of DRAM arrays and banks which leads into addressing data within a DRAM array; Defines banks, ranks and channels; Walks through the evolution of DRAM architecture (SDR, DDR1, DDR2, DDR3, DDR4, DDR4 and then on to LPDDR3, LPDDR4 and LPDDR5)
- Module 5: Packaging and HBM
- Introduces different package types (BGA, PoP, 3D Stacking, Die Stacking, TSI and Hybrid Memory Cube); Provides a brief discussion of High Bandwidth Memory (HBM)
- Module 6: DRAM Controller Basics and Addresses
- Discusses required blocks of a DRAM controller (address and control mux, refresh timer, PLL, timing generator, control registers, read and write buffer and IO buffer pads); Describes the translation necessary from system address to DRAM addressing, including symmetric vs asymmetric schemes and NUMA
- Module 7: DDR4 Device and DIMM Pin Descriptions
- Provides a description of the DDR4 device and DIMM pin groups as well as discusses changes in the JEDEC documentation styles to help avoid confusion when reading the standards
- Module 8: Intro to DIMMs (Dual Inline Memory Modules)
- Walks through the evolution of DIMMs from SIMMs to the various types of DIMMs (UDIMMs, RDIMMs, LRDIMMs, NVDIMMs, etc.)
- Module 9: Signal Routing
- Discusses basic signal routing rules and then walks through detailed examples of DDR4 fly-by routing for reads and writes
- Module 10: DDR4 - Bank State Machines, Commands and Waveforms
- Shows a detailed view of the DDR4 Bank States and discusses numerous state transitions, their motivations, behaviors, requirements, etc.; Contains a detailed table of DDR4 commands with descriptions; Walks through numerous DDR4 timing diagrams of various commands and provides insights for the motivations of behaviors and requirements; Also discusses burst orientations, types, lengths and order; Also discusses additive latency, NOP and power down
- Module 11: Refresh
- Provides a description of the different types of refresh and its history; Discusses important refresh timing parameters like Retention, Refresh Interval and Cycle Time; Describes the refresh command along with some newer forms of refresh (Temperature Controlled Refresh, Target Row Refresh, Refresh Management and Partial Array Refresh Control (PARC), and others), Row Hammer also discussed
- Module 12: DDR5, LPDDR4 and LPDDR5 Pin Descriptions
- Discusses Pin Groupings for DDR5, including additions/changes from DDR4; Similar discussion for LPDDR4 and LPDDR5 pin groupings
- Module 13: DDR5 Dual In-line Memory Modules
- Shows example diagrams of a 2 rank/channel DDR5 RDIMM and a 2 rank/channel DDR5 LRDIMM, also describes differences between UDIMMs and L/RDIMMs; Discusses DDR5 DIMM pinouts; DDR4 and DDR5 mirroring and inversion of command and address
- Module 14: DDR5 PMIC and the Sideband Bus
- Introduces the need for the Power Management IC (PMIC) and SidebandBus (I3C); explains limitations of I2C; shows several example systems and how PMICs and I3C fit in as well as typical communication with and behavior of PMICs
- Module 15: Non-Volatile DIMM Introduction
- Introduces NVDIMMs and the advantages / disadvantages of NVDIMMs vs other common DIMM types
- Module 16: DDR5 - Bank State Machines, Commands and Waveforms
- Detailed description of the DDR5 Bank states and the state transitions; Walks through the DDR5 commands and well as DDR5 burst order and behavior; Provides several examples of DDR5 command timing diagrams including DDR5 2N Mode
- Module 17: LPDDR4 - Bank State Machines, Commands and Waveforms
- Detailed description of the LPDDR4 Bank states and the state transitions; Walks through the LPDDR4 commands and provides several examples of LPDDR4 command timing diagrams including LPDDR4 MWR and DBI
- Module 18: LPDDR5 - Bank State Machines, Commands and Waveforms
- Detailed description of the LPDDR5 Bank states and the state transitions; Walks through the LPDDR5 commands and provides several examples of LPDDR5 command timing diagrams including WCK2CK Sync
- Module 19: Electrical Specifications
- Discusses numerous electrical aspects of modern DRAM including stub series-terminated logic, IDD current parameters, DDR5 IDD specs
- Module 20: Power Management
- Describes power down and self-refresh, numerous additional power savings modes, maximum power saving mode, clock throttling, frequency set points (FSP), dynamic voltage and frequency scaling (DVFSC and DVFSQ), Deep Sleep Mode
- Module 21: Signal Integrity Issues
- Discusses some of the most important items related to signal integrity
- Module 22: On-Die Termination
- Explains why ODT is needed and walks through the evolution of ODT for DRAM; Discusses ODT modes as well as Non-Target ODT (NT-ODT) and related mode registers
- Module 23: JEDEC Initialization
- Discusses the terms Initialization vs Training, SPD ROM location and format (with an example), mode registers and how to access, multi-purpose commands, Per-DRAM addressability (PDA); Goes through a detailed description of DDR 4 Mode Registers and Initialization process; Then walks through the steps for DDR5, LPDDR4 and LPDDR5 initialization as well
- Module 24: Calibration and Training
- Introduces the calibration features and then dives into ZQ calibration, Vref training, CA (Command Bus) training, duty cycle monitor and adjuster, read DQ calibration, write leveling, write calibration, FIFO-based training, DQS oscillator, Decision Feedback Equalization (DFE), DDR5 loopback
- Module 25: Errors and Error Handling
- Error Checking and Correction (ECC), DDR5 on-die ECC, ECC Error Check and Scrub (ECS), parity, CRC, post package repair (PPR), redundancy, guard key, Memory Built-In Self-Test (MBIST)
- Module 26: Testing
- JEDEC tools, types of tests and faults, structural testing, functional test, parametric and diagnostic tests, system, burn-in and stress tests, DDR4 and DDR5 connectivity test mode
- Module 27: Thank You!
- Much gratitude
- Module 28: Appendix: Additional DDR4 Waveforms
- Explains and shows timing diagrams for numerous DDR4 transactions
- Module 29: Appendix: Intel Toggle-Mode Interleaving
- Explains and shows examples of banks and toggle-mode addressing
- Module 30: Appendix: SMBus Overview
- Provides a brief introduction to SMBus behavior
 | Course Modules |
| Module | Length | | Module 1: Introduction and Outline | 41 minutes | | Module 2: System Architecture | 33 minutes | | Module 3: Intro to DRAM | 33 minutes | | Module 4a: DRAM Device Architecture | 37 minutes | | Module 4b: DRAM Device Architecture | 27 minutes | | Module 4c: DRAM Device Architecture | 32 minutes | | Module 4d: DRAM Device Architecture | 38 minutes | | Module 4e: DRAM Device Architecture | 37 minutes | | Module 5: Packaging and HBM | 32 minutes | | Module 6a: DRAM Controller Basics and Addresses | 22 minutes | | Module 6b: DRAM Controller Basics and Addresses | 28 minutes | | Module 7a: DDR4 Device and DIMM Pin Descriptions | 39 minutes | | Module 7b: DDR4 Device and DIMM Pin Descriptions | 33 minutes | | Module 8a: Intro to DIMMs (Dual Inline Memory Modules) | 30 minutes | | Module 8b: Intro to DIMMs (Dual Inline Memory Modules) | 29 minutes | | Module 9: Signal Routing | 36 minutes | | Module 10a: DDR4 - Bank State Machines, Commands and Waveforms | 33 minutes | | Module 10b: DDR4 - Bank State Machines, Commands and Waveforms | 19 minutes | | Module 10c: DDR4 - Bank State Machines, Commands and Waveforms | 24 minutes | | Module 10d: DDR4 - Bank State Machines, Commands and Waveforms | 44 minutes | | Module 10e: DDR4 - Bank State Machines, Commands and Waveforms | 23 minutes | | Module 11a: Refresh | 36 minutes | | Module 11b: Refresh | 37 minutes | | Module 11c: Refresh | 50 minutes | | Module 12: DDR5, LPDDR4 and LPDDR5 Pin Descriptions | 34 minutes | | Module 13a: DDR5 Dual In-line Memory Modules | 43 minutes | | Module 13b: DDR5 Dual In-line Memory Modules | 18 minutes | | Module 14a: DDR5 PMIC and the Sideband Bus | 33 minutes | | Module 14b: DDR5 PMIC and the Sideband Bus | 39 minutes | | Module 14c: DDR5 PMIC and the Sideband Bus | 42 minutes | | Module 14d: DDR5 PMIC and the Sideband Bus | 18 minutes | | Module 15: Non-Volatile DIMM Introduction | 38 minutes | | Module 16a: DDR5 - Bank State Machines, Commands and Waveforms | 21 minutes | | Module 16b: DDR5 - Bank State Machines, Commands and Waveforms | 28 minutes | | Module 16c: DDR5 - Bank State Machines, Commands and Waveforms | 34 minutes | | Module 16d: DDR5 - Bank State Machines, Commands and Waveforms | 20 minutes | | Module 16e: DDR5 - Bank State Machines, Commands and Waveforms | 33 minutes | | Module 17a: LPDDR4 - Bank State Machines, Commands and Waveforms | 23 minutes | | Module 17b: LPDDR4 - Bank State Machines, Commands and Waveforms | 21 minutes | | Module 17c: LPDDR4 - Bank State Machines, Commands and Waveforms | 22 minutes | | Module 17d: LPDDR4 - Bank State Machines, Commands and Waveforms | 28 minutes | | Module 18a: LPDDR5 - Bank State Machines, Commands and Waveforms | 26 minutes | | Module 18b: LPDDR5 - Bank State Machines, Commands and Waveforms | 28 minutes | | Module 18c: LPDDR5 - Bank State Machines, Commands and Waveforms | 28 minutes | | Module 18d: LPDDR5 - Bank State Machines, Commands and Waveforms | 23 minutes | | Module 18e: LPDDR5 - Bank State Machines, Commands and Waveforms | 20 minutes | | Module 18f: LPDDR5 - Bank State Machines, Commands and Waveforms | 22 minutes | | Module 19: Electrical Specifications | 36 minutes | | Module 20a: Power Management | 17 minutes | | Module 20b: Power Management | 29 minutes | | Module 20c: Power Management | 29 minutes | | Module 20d: Power Management | 11 minutes | | Module 21: Signal Integrity Issues | 14 minutes | | Module 22a: On-Die Termination | 32 minutes | | Module 22b: On-Die Termination | 28 minutes | | Module 22c: On-Die Termination | 39 minutes | | Module 23a: JEDEC Initialization | 39 minutes | | Module 23b: JEDEC Initialization | 34 minutes | | Module 23c: JEDEC Initialization | 31 minutes | | Module 23d: JEDEC Initialization | 34 minutes | | Module 24a: Calibration and Training (Introduction) | 6 minutes | | Module 24b: Calibration and Training (ZQ Calibration) | 24 minutes | | Module 24c: Calibration and Training (ZQ Calibration) | 24 minutes | | Module 24d: Calibration and Training (Vref Training) | 29 minutes | | Module 24e: Calibration and Training (Command Bus Training) | 30 minutes | | Module 24f: Calibration and Training (Command Bus Training) | 13 minutes | | Module 24g: Calibration and Training (Command Bus Training) | 30 minutes | | Module 24h: Calibration and Training (Duty Cycle Adjuster) | 40 minutes | | Module 24i: Calibration and Training (Duty Cycle Adjuster) | 20 minutes | | Module 24j: Calibration and Training (Read Calibration) | 23 minutes | | Module 24k: Calibration and Training (Read Calibration) | 31 minutes | | Module 24l: Calibration and Training (Write Leveling) | 35 minutes | | Module 24m: Calibration and Training (Write Calibration) | 20 minutes | | Module 24n: Calibration and Training (Decision Feedback Equalization) | 26 minutes | | Module 24o: Calibration and Training (DDR5 Loopback) | 24 minutes | | Module 25a: Errors and Error Handling | 22 minutes | | Module 25b: Errors and Error Handling | 25 minutes | | Module 25c: Errors and Error Handling | 21 minutes | | Module 25d: Errors and Error Handling | 11 minutes | | Module 25e: Errors and Error Handling | 31 minutes | | Module 26a: Testing | 34 minutes | | Module 26b: Testing | 24 minutes | | Module 27: Thank You! | 1 minutes | | Module 28: Appendix: Additional DDR4 Waveforms | 40 minutes | | Module 29: Appendix: Intel Toggle-Mode Interleaving | 12 minutes | | Module 30: Appendix: SMBus Overview | 29 minutes | | |
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