NVM Express 1.2a eLearning Course

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NVM Express 1.2a eLearning Course

Instructor(s): Mike Jackson
Number of Modules: 19
Subscription Length: 90 days

Course Price
$395.00
Bundle Price (Course & Arbor)
$895.00
(more info on Arbor)



NVM Express 1.2a Technology eLearning Course

What's Included?

NVMe eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)
PCI Express eBook
(yours to keep, does not expire)

Benefits of eLearning:

  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready

Who Should View?

This in-depth course is designed with the hardware or software engineer in mind. The course contains a detailed description of the NVM controller interface, the submission queues, completion queues and how software and the controller communicate with each other.

Course Outline:

  • Module 1: Introduction to NVMe
    - Motivation for NVMe, big picture (commands, submission queues, completion queues, etc.)
  • Module 2: NVMe Host-Controller Interface
    - Topology, NVMe controller registers, establishing admin queue, control registers and initialization, NVMe labs using Arbor
  • Module 3: Queue Management
    - Queue Doorbell pointers and usage, queueing commands, fetching commands, writing completions, notifying host, tracking completion queue entries
  • Module 4: NVMe Commands
    - Identify command, Create IO Completion Queue command, Create IO Submission Queue command, NVMe labs using Arbor
  • Module 5: NVMe Command Execution and Arbitration
    - Creating and submitting commands, notifying controller, controller fetching commands and writing completions, phase tag information, round robin and weighted round robin (WRR) command arbitration
  • Module 6: Addressing Models: PRP and SGL
    - Commands using Physical Region Pages (PRPs), Commands using Scatter/Gather Lists (SGLs), PRP lists, SGL elements, SGL descriptors
  • Module 7a: Get Features and Set Features Commands
    - Purpose of Get Features and Set Features commands, feature identifiers, feature numbers to set, temperature threshold
  • Module 7b: Get Features and Set Features Commands
    - NVMe labs using Arbor
  • Module 8: Error Reporting and Handling
    - Error reporting and handling, Asynchronous Event Requests (AERs), completion error reporting and handling, admin commands, abort commands, Log page
  • Module 9: Firmware Updates
    - Firmware update process including live updates, Firmware image download, Firmware commit
  • Module 10: Controller Registers
    - Capability, Control, Status register, Doorbell register and more. Memory buffer support
  • Module 11: Controller Architecture
    - Controller initialization, resets (controller-level reset, queue-level reset), queue management, interrupts, interrupt coalescing
  • Module 12: Power Management
    - PCIe power options, NVM power states, changing power states, autonomous power state change, Runtime D3
  • Module 13: Reservations
    - Method of reservations, NVM commands for reservations (Report, Register, Acquire, Release), Namespace management and creating Namespaces, unregistering, acquiring and releasing reservation
  • Module 14: Appendix A: Summary of Changes for v1.2 and v1.2a
    - Host memory buffer, runtime D3, workload hints, re-play memory block, namespace management, live firmware update, temperature thresholds, control memory buffer
  • Module 15: Appendix B: Other NVMe Commands
    - Read command, Write command, Write Uncorrectable command, Compare command, Dataset Management command, Identify command (and detailed results), Namespace data, Protection Information (PI)
  • Module 16a: Appendix C: PCIe Architecture Overview
    - Links vs Lanes, bandwidth, Root Complex, Switches, Endpoints, PCIe device layers
  • Module 16b: Appendix C: PCIe Architecture Overview
    - PCIe device layers (Transaction), Transaction Layer Packets (TLPs), QoS, Flow Control
  • Module 16c: Appendix C: PCIe Architecture Overview
    - PCIe device layers (Data Link, Physical), Data Link Layer Packets (DLLPs), Ack/Nak Protocol, Ordered Sets, configuration space
Course Modules
ModuleLength
Module 1: Introduction to NVMe30 minutes
Module 2: NVMe Host-Controller Interface23 minutes
Module 3: Queue Management19 minutes
Module 4: NVMe Commands49 minutes
Module 5: NVMe Command Execution and Arbitration22 minutes
Module 6: Addressing Models: PRP and SGL21 minutes
Module 7a: Get Features and Set Features Commands24 minutes
Module 7b: Get Features and Set Features Commands9 minutes
Module 8: Error Reporting and Handling 48 minutes
Module 9: Firmware Updates9 minutes
Module 10: Controller Registers25 minutes
Module 11: Controller Architecture18 minutes
Module 12: Power Management11 minutes
Module 13: Reservations28 minutes
Module 14: Appendix A: Summary of Changes for v1.2 and v1.2a11 minutes
Module 15: Appendix B: Other NVMe Commands 37 minutes
Module 16a: Appendix C: PCIe Architecture Overview30 minutes
Module 16b: Appendix C: PCIe Architecture Overview26 minutes
Module 16c: Appendix C: PCIe Architecture Overview26 minutes