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PCIe6 Update eLearning Course Info
What's Included?
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PCIe6 Update eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
You Will Learn:
- PAM4 signaling
- The need for Forward Error Correction
- Behavior of the Physical Layer at 64GT/s
- Flit format
- Ack/Nak protocol at the Flit level
- Shared vs Dedicated Flow Control Buffers
- TLP Format while in Flit Mode
- The need for Segments in some TLPs
- Benefits and operation of L0p
Who Should View?
This course is for anyone who has a solid understanding of PCIe 5.0 and would like to quickly get up-to-speed on PCIe 6.0.
Course Outline:
- Module 1: Course Intro
- Introduction to the course and explanation of the ordering of topics
- Module 2a-2b: Introduction to PCIe6
- Provides a high-level overview of several of the changes that come with PCIe6: 64GT/s, PAM4 signaling, Flit Mode and definition of Flits, Forward Error Correction (ECCs), impacts of Flit Mode (FM) on upper layers
- Module 3a-3c: 1b/1b Physical Layer
- Detailed look at PAM4 signaling and how 64GT/s is achieved, precoding (addressing burst errors or error propagation), gray coding, scrambling, half-scrambling, ordered set format and use during 1b/1b operation, byte striping
- Modules 4a-4c: LTSSM Updates
- Discusses the updates to the LTSSM for Gen6; how and when Flit Mode is entered, ordered set insertion rules, changes to Tx equalization
- Module 5: Flit Mode Logical Physical Layer
- More description of the CRC per Flit as well as the Forward Error Correction (ECC) protection per Flit
- Modules 6a-6g: Flit Mode Data Link Layer
- Provides detailed discussion of the DLP bytes per Flit, IDLE vs NOP vs Payload Flits, Sequence numbers in Flit Mode, entering Flit Mode from Config and Recovery states of LTSSM, standard replay vs selective replay with numerous examples, new DLLPs for FM (Link Management DLLP, Flit_Marker, Optimized_Update_FC)
- Modules 7: Flit Mode Transaction Layer: TLP Packing/Unpacking
- Shows how TLPs get packed and unpacked within Flits
- Modules 8a-8d: Flit Mode Transaction Layer: Flow Control
- Discusses the optional new Shared buffers defined in FM, credit blocks, tracking credits and the flow control update process, usage limit enabled vs disabled behavior, merged FC, flow control initialization and requirements
- Modules 9a-9c: Flit Mode Transaction Layer: TLP Format
- Shows how TLPs get packed within Flits, provides detailed description of new TLP format in FM (Local prefix(es), header base, OHC (Orthogonal Header Content), data, TLP trailer), format of each type of OHC and when they should be used, format and size of each type of TLP trailer
- Module 10: Flit Mode Segments
- Introduces the concept of Segments and then gives examples of why they are needed, discusses Segment info being required in all configuration transactions, dealing with systems that may have some links in FM vs others in NFM and how that affects segment info
- Module 11: Flit Mode L0p
- Discusses the behavior of L0p and its usefulness to help save power without ever leaving L0; transitioning into and out of L0p
- Module 12a-12b: PCIe6 Configuration Structure Updates
- Provides overviews of the following config structures: Physical Layer 64.0GT/s, Flit Logging, Flit Performance Measurement, Flit Error Injection, Device 3, Shadow Functions
 | Course Modules |
| Module | Length | | Module 1: Course Intro | 27 minutes | | Module 2a: Introduction to PCIe6 | 25 minutes | | Module 2b: Introduction to PCIe6 | 33 minutes | | Module 3a: 1b/1b Physical Layer | 29 minutes | | Module 3b: 1b/1b Physical Layer | 28 minutes | | Module 3c: 1b/1b Physical Layer | 40 minutes | | Module 4a: LTSSM Updates | 30 minutes | | Module 4b: LTSSM Updates | 22 minutes | | Module 4c: LTSSM Updates | 18 minutes | | Module 5: Flit Mode Logical Physical Layer | 22 minutes | | Module 6a: Flit Mode Data Link Layer | 23 minutes | | Module 6b: Flit Mode Data Link Layer | 30 minutes | | Module 6c: Flit Mode Data Link Layer | 20 minutes | | Module 6d: Flit Mode Data Link Layer | 57 minutes | | Module 6e: Flit Mode Data Link Layer | 30 minutes | | Module 6f: Flit Mode Data Link Layer | 37 minutes | | Module 6g: Flit Mode Data Link Layer | 39 minutes | | Module 7: Flit Mode Transaction Layer: TLP Packing/Unpacking | 28 minutes | | Module 8a: Flit Mode Transaction Layer: Flow Control | 32 minutes | | Module 8b: Flit Mode Transaction Layer: Flow Control | 51 minutes | | Module 8c: Flit Mode Transaction Layer: Flow Control | 24 minutes | | Module 8d: Flit Mode Transaction Layer: Flow Control | 35 minutes | | Module 9a: Flit Mode Transaction Layer: TLP Format
| 16 minutes | | Module 9b: Flit Mode Transaction Layer: TLP Format
| 20 minutes | | Module 9c: Flit Mode Transaction Layer: TLP Format
| 22 minutes | | Module 10a: Flit Mode Segments
| 20 minutes | | Module 10b: Flit Mode Segments | 22 minutes | | Module 11: Flit Mode L0p | 33 minutes | | Module 12a: PCIe6 Configuration Structure Updates | 26 minutes | | Module 12b: PCIe6 Configuration Structure Updates | 39 minutes | | |
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