PCIe 4.0 Update

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PCIe 4.0 Update

Instructor(s): Joe Winkles
Number of Modules: 8
Subscription Length: 90 days

Pre-Order Price: $295.00
Regular Price: $395.00
(release date: August 2018)

PCIe 4.0 Update

What's Included?

PCIe 4.0 Update eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)

Benefits of eLearning:

  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready

Who Should View?

This course is meant for any hardware or software engineers that already have a strong working knowledge of PCIe 3.x and just want to find out the new pieces introduced in the PCIe 4.0 spec.

Course Outline:

  • Module 1: PCIe 4.0 Intro, 10-bit Tags and Extended MSI Data
    - Introduction to PCIe 4.0 speed changes (16.0 GT/s), new and expanded fields of TLPs (e.g. 10-bit Tags) and coverage of extended MSI data field in interrupts
  • Module 2: Scaled Flow Control
    - Review of normal flow control, introduction of scaled flow control, motivation for scaled flow control, new Data Link Feature DLLPs, updates to DLCMSM state machine, example credit exchange with scaled flow control
  • Module 3: New DLLPs and Ack/Nak Changes
    - Introduction of new DLLPs, review of the Ack / Nak protocol, updates to the Replay Timer (simplified replay timer limit)
  • Module 4: Updates to Logical PHY and Link Training
    - Review of 128/130b, introduction of new Control SKP Ordered Set, data parity checking at 8.0GT/s and changes for data parity checking at 16.0GT/s, review of 3-tap equalizer used for Tx Equalization, intro to new Physical Layer 16.0GT/s Extended Capability structure
  • Module 5: Retimers
    - Intro to Retimers, definition of link segments and pseudo-ports, forwarding mode and execution mode, what retimers can modify, handling electrical idle, handling training of links (and link segments) with a focus on Tx equalization
  • Module 6: Lane Margining
    - Intro to lane margining, time margining concept, voltage margining concept, Lane Margining Extended Capability structure, initiating margining commands, performing lane margining on a retimer (Control SKP ordered sets)
  • Module 7: Flattening Portal Bridges (FPB)
    - Static allocation limits, removing the designated bus number within a switch, dynamic allocation limits, FPB Routing ID vector and FPB Memory routing vector, solution for hot plug environments
  • Module 8: Heirarchy ID, DVSEC, Enhanced Allocation and Emergency Power Reduction
    - Intro to Hierarchy ID messages and capability structure, intro to Desgnated Vendor-Specific (DVSEC) feature, intro to Enhanced Allocation feature (for embedded environments), intro to Emergency Power Reduction State
Course Modules
Coming Soon!