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PIPE 6.0 - PHY Interface for PCI Express and more
Instructor(s): Mike Jackson
Number of Modules: 14
Subscription Length: 90 days
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Course Price
$395.00 |
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PIPE 6.0 eLearning Course
What's Included?
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PIPE eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
Who Should View?
This in-depth course is for anyone looking to understand PIPE (PHY Interface for PCI Express, SATA, USB3.1, DisplayPort and USB4), its signals and how it is used for different protocols.
Course Outline:
- Module 1: Introduction
- Intro to PIPE, Original PIPE vs SerDes PIPE, PCLK options, data throttling, Message Bus intro, interface types (legacy vs low pint count, LPC), registers in MAC and PHY, combining PIPEs for multi-lane link
- Module 2a: PHY/MAC Interface (Intro)
- Interface support options, Short-Reach (SR) applications, terminology of signal names in spec
- Module 2b: PHY/MAC Interface (Common Signals)
- External signals, command signals, command interface inputs to PHY, SRIS motivation, power states, receiver detection, command interface status outputs, PHY status signals (inputs and output), data signal, block synchronization, original PIPE block diagrams
- Module 2c: PHY/MAC Interface (Original and SerDes specific signals)
- SerDes signals, original PIPE signals, Message Bus, Message Bus commands, command formats, Message Bus rules
- Module 3: PHY Registers
- PHY register list, register definitions, register groups, intro to equalization, PCIe EQ starting parameters, delivering Tx FS/LF values, speed change example, getting local coefficients example, updating PHY Tx values
- Module 4: MAC Registers
- Elastic buffer registers, signal integrity, PHY recalibration, link equalization evaluation, Gen5 Tx parameters, local preset values, Gen3 and Gen4 Tx parameters
- Module 5: PIPE Operational Behavior: PCIe Mode
- Key features, voltage margining, Tx options (e.g. low voltage), de-emphasis intro and setting de-emphasis value, Inter-Symbol Interference (ISI)
- Module 6a: Equalization Process
- Equalization commonalities across protocols, 3-tap equalizer, preset encodings, effect of Tx equalization, location of EQ circuitry and logic, initializing preset values, fetching PHY Tx values for preset(s), Tx equalizer values, relationship between coefficients and FS, MAC tells PHY what coefficients to use, MAC applies coefficients
- Module 6b: Equalization Process
- Equalization phase summary, EQ phase 1 step through, EQ phase 2 step through, accepting vs rejecting coefficients, EQ phase 3 step through, Tx EQ finishing, Rx equalization
- Module 7: PCIe Lane Margining
- Lane margining background, time margining concept, voltage margining concept, SW in control of margining, related configuration registers for PCIe, location of config space, margining register encodings for PCIe, determining what's an error, step time margin command, step voltage margin command, step margin command response, dependent vs independent samplers, affected PHY registers, margining a retimer, receiver numbers, affected MAC registers
- Module 8: PCIe Elastic Buffer
- Purpose of elastic buffer, nominal half-full buffer, adding / removing SKPs (skips), nominal empty buffer, PHY elastic buffer registers
- Module 9: PCIe Power States
- Intro to power states, timing diagrams for L0 to L0s entry and exit, timing diagram for L0 to L1 entry and exit, L1 substates, receiving electrical idle
- Module 10: PIPE Operational Behavior: USB Mode
- Key features, USB power states, low frequency periodic signaling (LFPS), variants of LFPS, receiver detection, USB equalization, forcing compliance patterns
- Module 11: PIPE Operational Behavior: SATA Mode
- Key features, Out of Band (OOB) signaling, OOB and alignment, SATA speed negotiation, SATA power states
 | Course Modules |
| Module | Length | | Module 1: Introduction | 32 minutes | | Module 2a: PHY/MAC Interface | 7 minutes | | Module 2b: PHY/MAC Interface | 48 minutes | | Module 2c: PHY/MAC Interface | 19 minutes | | Module 3: PHY Registers | 20 minutes | | Module 4: MAC Registers | 9 minutes | | Module 5: PIPE Operational Behavior: PCIe Mode | 15 minutes | | Module 6a: Equalization Process | 36 minutes | | Module 6b: Equalization Process | 31 minutes | | Module 7: PCIe Lane Margining | 28 minutes | | Module 8: PCIe Elastic Buffer | 9 minutes | | Module 9: PCIe Power States | 13 minutes | | Module 10: PIPE Operational Behavior: USB Mode | 9 minutes | | Module 11: PIPE Operational Behavior: SATA Mode | 10 minutes | | |
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