x86 Architecture eLearning Course

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x86 Architecture eLearning Course

Instructor(s): Joe Winkles
Number of Modules: 21
Subscription Length: 90 days

Course Price
$595.00



x86 Architecture eLearning Course

Note: this course is a subset of our Intel Processor and Platform eLearning Course

What's Included?

Course eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)
x86 ISA eBook
(yours to keep, does not expire)

Benefits of eLearning:

  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready

Who Should View?

This course will be useful for anyone dealing with designing, verifying, validating, debugging, or developing for x86-based platforms. The x86 instruction set architecture has evolved over a period of almost 40 years. This course describes numerous aspects of the current architecture but also explains how we got to the current architecture based on the history and decisions made. It doesn't matter whether you're a hardware engineer or a software developer, this course has an enormous amount of relevant info for you.

Course Outline:

  • Module 1: Course Introduction
    - Scope of course
  • Module 2: x86 Instruction Set Overview
    - x86 instruction basics, instruction variants, integer operations, floating-point operations, MMX, SSE, AVX, program flow-related instructions, hardware-related instructions, x86 instruction format
  • Module 3: x86 Register Set Introduction
    - Registers per thread (logical processor), general-purpose registers, flags register, x87 registers, MMX registers, XMM registers, YMM registers, ZMM registers, segment registers, control registers, debug registers, model-specific registers (MSRs)
  • Module 4: x86 CPU Operating Modes
    - Real Mode, (legacy) Protected Mode, Virtual-8086 Mode, System Management Mode, Compatibility Mode, 64-bit Mode, Long Mode (IA-32e Mode) vs Legacy Mode
  • Module 5: Platform Addressing
    - Memory space (system memory vs. memory-mapped IO: MMIO), IO space, PCI config space
  • Module 6a: CPU Memory Segmentation Part A
    - Memory accesses, address generation (effective address, logical address, linear/virtual address, physical address), Real Mode segmentation
  • Module 6b: CPU Memory Segmentation Part A
    - Code and Data segment descriptors, Global Descriptor Table (GDT), Local Descriptor Tables (LDTs), descriptor cache, flat memory model, Intel64 segmentation, long bit (CS.L)
  • Module 7a: Paging and TLBs
    - Paging concepts and basic paging implementation in x86 architecture, on-demand paging example
  • Module 7b: Paging and TLBs
    - x86 paging facts and page sizes: 4KB, 2MB, 4MB, 1GB, details of PTE, PDE, PDPE, PML4E, Page Size Extensions (PSE), Physical Address Extensions (PAE), Long Mode paging (Page Map Level 4 - PML4), intro to Processor Context ID (PCID), paging access rights determination, protection keys, execute disable (aka no execute)
  • Module 7c: Paging and TLBs
    - Purpose of Translation Lookaside Buffers (TLBs), TLB behavior, global pages, contents of TLB entry, managing TLBs (INVLPG, INVPCID, INVVPID, MOV CR0, CR3, CR4), TLB shootdowns
  • Module 8: Interrupts - Intro and Controller History
    - Intro to interrupt handling, hardware interrupts vs software interrupts vs exceptions, interrupt vectors, locating handler via Interrupt Descriptor Table, 8259A interrupt controller basics, intro to APIC / IO APIC and xAPIC
  • Module 9: Interrupts - Local APIC Basics
    - Local APIC registers, x2APIC, priority among hardware interrupts, masking interrupts based on priority threshold (TPR), behavior of local APIC
  • Module 10: Interrupts - Delivery Options
    - APIC IDs (physical APID ID and logical APIC ID), physical destination mode, logical flat destination mode, logical cluster destination mode, redirectable interrupts, power aware interrupt remapping (PAIR)
  • Module 11: Interrupts - MSI, Interrupt Remapping and IPIs
    - Message Signaled Interrupts (MSI), address and data encodings for x86 platforms, setting up MSI info at devices (PCI config space), MSI-X, purpose of interrupt remapping and overview of concept, Inter-Processor Interrupts (IPIs)
  • Module 12a: Overview of Intel Virtualization Support
    - What is virtualization, different approaches (application level vs machine level), software solutions (ring deprivileging, binary translation, paravirtualization), Intel VT-x, virtual machine control structure (VMCS), Intel VT example usage
  • Module 12b: Overview of Intel Virtualization Support
    - Memory and virtualization (shadow page tables vs extended page tables - EPTs), intro to VT-d features (IO virtualization)
  • Module 13: CPU Performance Monitoring
    - Core performance monitoring, performance monitoring counters, fixed function vs general purpose monitoring, precise event based sampling (PEBS), uncore performance monitoring
  • Module 14: Machine Check Architecture (MCA)
    - MCA error detection and reporting, MCA error classes (corrected and uncorrected), MCA-related interrupts, MCA registers, MCA banks
  • Module 15a: System Management Mode (SMM)
    - Purpose of SMM, System Management Interrupt (SMI), sources of SMI
  • Module 15b: System Management Mode (SMM)
    - SMRAM, Multi-core / multi-CPU behavior, protecting SMRAM, SMM operation considerations, latency, security, cache management, setting up PCH for SMI, SMM example
  • Module 16: Intel Microcode Update
    - Need for microcode updating, update procedure
Course Modules
ModuleLength
Module 1: Course Introduction 19 minutes
Module 2: x86 Instruction Set Overview 54 minutes
Module 3: x86 Register Set Introduction 52 minutes
Module 4: x86 CPU Operating Modes 49 minutes
Module 5: Platform Addressing 39 minutes
Module 6a: CPU Memory Segmentation Part A 25 minutes
Module 6b: CPU Memory Segmentation Part B 56 minutes
Module 7a: x86 Paging and TLBs 45 minutes
Module 7b: x86 Paging and TLBs 52 minutes
Module 7c: x86 Paging and TLBs 53 minutes
Module 8: Interrupts: Intro and Controller History 48 minutes
Module 9: Interrupts: Local APIC Basics 38 minutes
Module 10: Interrupts: Delivery Options 34 minutes
Module 11: Interrupts: MSIs, Interrupt Remapping and IPIs 54 minutes
Module 12a: Overview of Virtualization Support 47 minutes
Module 12b: Overview of Virtualization Support 32 minutes
Module 13: CPU Performance Monitoring 43 minutes
Module 14: Machine Check Architecture (MCA) 44 minutes
Module 33a: System Management Mode (SMM) Details57 minutes
Module 33b: System Management Mode (SMM) Details63 minutes
Module 16: Microcode Update 13 minutes