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Training

Let MindShare Bring "Hands-On PCI Express 5.0 (Gen5)" to Life for You

MindShare's PCI Express System Architecture course starts with a high-level view of the technology to provide the big-picture context and then drills down into the details for each topic, providing a thorough understanding of the hardware and software protocols.

The course describes additional features added to the architecture when moving through the PCIe specification revisions from 1.1 all the way to the latest 5.0. There are a large number of features and optional behaviors described in the PCIe spec. MindShare can customize the course to cover the topics that are most important for your group. Use the course outline below as a guide to request topics you want covered or removed. The table below contains a list of suggested course customizations.

MindShare Courses On PCI Express 5.0, 4.0, 3.x, 2.x and 1.x:

Course Name
Classroom

Virtual Classroom

eLearning
Hands-On PCI Express 5.0 
5 days

5 days

Show Me
Core PCI Express 5.0 
4 days

4 days

Show Me
Advanced PCI Express 3.x, 4.0 and 5.0 Update 
3 day

3 day
Coming March 2021
PCI Express for Software Engineers 
3 day

3 day

Show Me
PCI Express 4.0 and 5.0 Update 
1 day

1 day
Coming March 2021
Fundamentals of PCI Express
1 day

1 day

Show Me
PIPE 6.0 - PHY Interface for PCI Express and more
1 day

1 day

Show Me
Hands-On NVMe 1.4 Architecture
2 day

2 day

Show Me
IO Virtualization for Intel Platforms
3 days

3 days

Show Me
IO Virtualization for ARM Platforms
3 days

3 days
Notify Me When Available  

All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.


Hands-On PCI Express 5.0 (Gen5) Course Info

You Will Learn:

  • PCI Express features and capabilities
  • The definition and responsibilities of each of the layers in the interface
  • The PCIe packet-based transaction protocol details
  • The error detection, reporting and possible correction mechanisms
  • The address space and packet-routing methods used
  • How the various power management techniques work
  • The details of the configuration registers that provide control and status visibility to software
  • Software enumeration process
  • The process of transmitter equalization necessary to operate at 8.0GT/s, 16.0GT/s and 32.0GT/s
  • The details of the LTSSM including the concepts important for each state
  • Essential features added to Gen4 and Gen5 specifications

For SRIOV and ATS related topics, which are now incorporated into the PCIe 4.0 spec, please request our 3-day IO Virtualization for Intel Platforms or IO Virtualization for ARM Platforms as these topics are NOT covered in this standard 5-day PCIe course. PIPE 6.0 spec related topics are also not covered but can be requested. We cover ECNs listed below upon request.

Who Should Attend?

This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Given the in-depth architecture and design details covered, the course is also suitable for chip-level and board-level validation engineers.

Course Length: 5 days (but can be customized to shorter duration)

Course Outline:

  5-day Class

4-day Class

PCI Architecture Background Foundation    
  PCI concepts important for understanding PCI Express X X
  Physical Address Spaces X X
  Traffic Types (System Memory, PIO and DMA) X X
  Typical System Transactions (NVMe Example) X X
PCI Express Features and Architecture Overview    
  Layered Architecture X X
  ARM example topology X X
  TLP, DLLP and Ordered Set Packet Format Overview X X
  Protocol Overview X X
Configuration Overview    
  Legacy and Enhanced Configuration Access Mechanism (ECAM) X X
  Type 0 and Type 1 Headers, Capability and Extended Capability Structures X X
  Bus Enumeration X X
  HANDS-ON ARBOR LAB: Scan your system and determine topology X X
Address Space and Transaction Routing    
  Clarification of Memory space X X
  System memory vs MMIO X X
  Prefetchable vs Non-prefetchable X X
  IO space X X
  Setting up the BARs as well as the Base and Limit registers X X
  Switch Routing Mechanism X X
  HANDS-ON ARBOR LAB: Debug problem with address mapping X X
TLP Format Details    
  Normal TLP fields X X
  TLP Prefixes X  
  Lightweight Notification and TPH / Steering Tags X  
  10-bit Tags X X
  PCI-SIG Vendor-Defined Messages X  
Quality of Service and Arbitration    
  TC/VC Mapping X overview
  VC Arbitration X overview
  Port Arbitration X overview
  Multi-function Arbitration X overview
Flow Control    
  Flow Control Protocol X overview
  Scaled Flow Control X overview
  Link Feature Exchange X overview
  Flow Control Initialization X overview
  Runtime Flow Control Update Mechanism X overview
Transaction Ordering    
  Simplified Ordering Table X X
  Relaxed and ID-Based Ordering X X
DLLP Format Details    
  DLLPs X X
  NOP & Data Link Feature DLLPs X  
ACK / NAK Protocol    
  TLP Error Recovery Mechanism X X
  Simplified Replay Timer X X
  Examples of Numerous Error Scenarios X X
  Nullified Packets and Cut-Through Mode Switches X X
Physical Layer Logic (2.5GT/s and 5.0GT/s)    
  Block Diagram X X
  Ordered Sets X X
  Byte Striping/Unstriping X X
  Scrambling/Unscambling X X
  8b/10b Encoding/Decoding X X
  Serializing/Deserializing X X
Physical Layer Logic (8.0GT/s, 16.0GT/s and 32.0GT/s)    
  128b/130b Encoding/Decoding X X
  Control SKPs X X
  Ordered-Set Blocks and Data Blocks X X
  Data Streams and Packet Framing X X
  Data Parity Checking X X
  16.0 & 32.0 GT/s Data Parity Checking X X
  Precoding X  
Physical Layer Electrical (all speeds)    
  Differential Tx / Rx X X
  2.5GT/s and 5.0GT/s De-emphasis X X
  8.0GT/s, 16.0GT/s and 32.0GT/s Equalization Concept X X
  Rx Equalization X X
  Electrical Conditions for different Link States X X
  Spread Spectrum Clocking (SSC) X  
  Separate Refclk Independent SSC (SRIS) X  
Link Initialization and Training (LTSSM)    
  Detect, Polling, Configuration, L0 States X X
  Recovery: Link Speed Change X X
  Recovery: Equalization Process X overview
  16.0 GT/s Equalization and Config Structures X overview
  Negotiation for skipping parts or all of Tx Equalization X  
  32.0 GT/s Equalization and Config Structures X  
  Recovery: Link Width Change    
  L0s, L1, L2, Hot Reset, Link Disable and Loopback States X overview
  Modified TS1 / TS2s and Alternate Protocol Negotiation X  
Interrupt Support    
  Legacy Interrupt Handling    
  MSI Interrupts X X
  32-bit MSI Data X X
  MSI-X Interrupts X X
  HANDS-ON ARBOR LAB: Investigate source of MSI(-X) interrupt and delivery X X
Error Detection and Handling    
  Correctable, Non-Fatal and Fatal Errors X X
  Advisory Non-Fatal Errors X X
  Error Subclass field for Correctable Error Messages    
  Advanced Error Reporting (AER) X X
  HANDS-ON ARBOR LAB: Determine source and error reporting mechanism X X
Power Management    
  Device Power States X X
  Link Power States X X
  L1 Substates X X
  Link Activation    
  Active State Power Management (ASPM) - hardware controlled X X
  Software Controlled Power Management X X
  Power Management Events (PME, Beacon and #WAKE) X  
  Dynamic Power Allocation (DPA)    
  Optimized Buffer Flush Fill (OBFF)    
  Latency Tolerance Reporting (LTR) X X
System Resets    
  Conventional Reset Mechanisms: Cold, Warm and Hot Reset X X
  Function Level Reset (FLR) X X
Features Introduced with PCIe 4.0    
  Retimers overview overview
  Lane Margining overview overview
  Flattening Portal Bridge (FPB) overview  
  Hierarchy ID Reporting    
  Designated Vendor-Specific Extended Capability (DVSEC) overview  
  Enhanced Allocation    
  Emergency Power Reduction State    
Features Introduced with PCIe 5.0    
  System Firmware Intermediary Support overview  
Other PCIe Features    
  Hot Plug    
  Power Budgeting    
  Multi-Casting    
  Protocol Multiplexing (PMUX)    
  Resizable BARs    
  Downstream Port Containment (DPC) and Enhanced DPC (eDPC)    
  Lightweight Notification (can be used for lightweight cache coherency)    
  Process Address Space ID (PASID)    
  Precision Time Measurement (PTM)    
  Device Readiness Status (DRS) and Function Readiness Status (FRS)    

Recommended Prerequisites:

A basic understanding of digital bus architectures such as PCI is recommended.

Training Materials:

1) MindShare will supply a copy of the "PCI Express Technology" eBook (covers PCIe 3.0) or hardcopy book on request

MindShare’s PCI Express Technology textbook (PCIe 3.0)
Authors: Mike Jackson and Ravi Budruk
Publisher: MindShare Press
Available through the MindShare Store and major bookstore outlets.

2) Downloadable PDF version of the presentation slides

3) Add-on MindShare Arbor software tool, used for student labs in the class (discounted pricing applies)

4) Add-on Comprehensive PCI Express 3.1 eLearning course (discounted pricing applies)

 




9am-5pm PST (California Time): 11/29/2021
9am-5pm PST (California Time): 11/29/2021

PCI Express Technology 3.0