[{"data":1,"prerenderedAt":83},["ShallowReactive",2],{"GET-live-training-course/slug/arm-64-bit-server-architecture-{}-{}":3},{"data":4},{"id":5,"name":6,"slug":7,"description":8,"about":9,"training_materials":10,"you_will_learn":11,"prerequisites":12,"is_active":13,"category_id":14,"duration":15,"modified_at":10,"course_outline":16,"supplied_materials":10,"thumbnail":17,"elearning_courses":18,"ebooks":65,"topics":66,"reviews":82,"meta_title":10,"meta_description":10,"meta_keywords":10},713,"ARM 64-bit Server Architecture","arm-64-bit-server-architecture","\u003Cp>This course describes the architecture of ARM’s 64-bit processors and SoC architecture. Examples of SoCs that implement this 64-bit architecture are the ARM Cortex-A53 and Cortex A57 processors. The courses covers the ISA (Instruction Set Architecture) details, pipeline information for some implementations of the v8A architecture, interconnect details, cache management, and power management.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(186, 55, 42);\">\u003Cstrong>All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.\u003C/strong>\u003C/span>\u003C/p>","\u003Cp class=\"sectionsubhead\">\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARM 64-bit Server Architecture\" to Life for You\u003C/strong>\u003C/span>\u003C/p>",null,"\u003Cul>\r\n\u003Cli>ARM architecture (ARMv8-A and v9-A)\u003C/li>\r\n\u003Cli>64-bit ISA (registers, instruction set etc)\u003C/li>\r\n\u003Cli>Memory and paging architecture\u003C/li>\r\n\u003Cli>Exception and Interrupt handling\u003C/li>\r\n\u003Cli>Pipeline implementations\u003C/li>\r\n\u003Cli>Cache management\u003C/li>\r\n\u003Cli>System interconnects\u003C/li>\r\n\u003Cli>Power management\u003C/li>\r\n\u003Cli>Server specific SoC features\u003C/li>\r\n\u003C/ul>","\u003Cp>Knowledge of ARMv7 32-bit architecture is recommended.\u003C/p>",true,3,"4 days","\u003Cul>\r\n\u003Cli>Introduction to ARM 64-bit Architecture\u003C/li>\r\n\u003Cli>ARM architecture profiles, what is v8-A and v9-A\u003C/li>\r\n\u003Cli>v8-A introduction and rational\u003C/li>\r\n\u003Cli>Support for v7 legacy code\u003C/li>\r\n\u003Cli>64-bit platform architecture overview\u003Cbr>\r\n\u003Cul>\r\n\u003Cli>Sample SoC\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>A64 ISA introduction\u003C/li>\r\n\u003Cli>Integer registers\u003C/li>\r\n\u003Cli>Instruction set\r\n\u003Cul>\r\n\u003Cli>Integer operations\u003C/li>\r\n\u003Cli>Memory operations\u003C/li>\r\n\u003Cli>Stack\u003C/li>\r\n\u003Cli>System instructions\r\n\u003Cul>\r\n\u003Cli>System control registers\u003C/li>\r\n\u003Cli>Relationship to v7 support and co-processors\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Calling conventions\u003C/li>\r\n\u003Cli>Memory access (DRAM and device)\r\n\u003Cul>\r\n\u003Cli>Memory mapped access to devices\u003C/li>\r\n\u003Cli>Memory types\u003C/li>\r\n\u003Cli>Ordering model\u003C/li>\r\n\u003Cli>Barriers\r\n\u003Cul>\r\n\u003Cli>dmb, dsb, isb\u003C/li>\r\n\u003Cli>load-acquire and store-release\u003C/li>\r\n\u003Cli>Domains\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Semaphores\u003C/li>\r\n\u003Cli>Cache management\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Floating point, advanced SIMD, crypto\r\n\u003Cul>\r\n\u003Cli>Registers and instructions\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Exception levels\r\n\u003Cul>\r\n\u003Cli>The 4 exception levels\u003C/li>\r\n\u003Cli>Stack model, handler and thread\u003C/li>\r\n\u003Cli>Vector table\u003C/li>\r\n\u003Cli>Core implementation choices\u003C/li>\r\n\u003Cli>Switching AArch32 and AArch64 state\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Exception and interrupt handling\r\n\u003Cul>\r\n\u003Cli>Control of delivery of exceptions and interrupts\u003C/li>\r\n\u003Cli>Syndrome registers\u003C/li>\r\n\u003Cli>Switching exception levels\u003C/li>\r\n\u003Cli>Return from exception\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Paging\r\n\u003Cul>\r\n\u003Cli>Page tables\u003C/li>\r\n\u003Cli>4K, 16K and 64K granules\u003C/li>\r\n\u003Cli>Page sizes, support for large pages\u003C/li>\r\n\u003Cli>TLB management\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Caches\r\n\u003Cul>\r\n\u003Cli>Cache architecture\u003C/li>\r\n\u003Cli>Multiple cache levels\u003C/li>\r\n\u003Cli>Instruction and data/unified caches\u003C/li>\r\n\u003Cli>Hardware cache coherency, MP Core and multi-cluster\u003C/li>\r\n\u003Cli>Shareability domains\u003C/li>\r\n\u003Cli>I/O cache coherency\u003C/li>\r\n\u003Cli>Software responsibilities\u003C/li>\r\n\u003Cli>Cache control\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Security (TrustZone)\r\n\u003Cul>\r\n\u003Cli>Trustzone overview\u003C/li>\r\n\u003Cli>Switching bitness of TrustZone between 32-bit and 64-bit\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Virtualization overview\u003C/li>\r\n\u003Cli>ARM Piplelines\r\n\u003Cul>\r\n\u003Cli>Cortex-A57\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Interconnects and multi-core support\r\n\u003Cul>\r\n\u003Cli>MP Core\u003C/li>\r\n\u003Cli>Role of the interconnect\u003C/li>\r\n\u003Cli>Cache oherency and the interconnect\u003C/li>\r\n\u003Cli>DVM and the interconnect\u003C/li>\r\n\u003Cli>Role of the interconnect in memory ordering models\u003C/li>\r\n\u003Cli>CHI\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Interrupt architectures\r\n\u003Cul>\r\n\u003Cli>Interrupt delivery across multiple cores\u003C/li>\r\n\u003Cli>Software generated interrupts\u003C/li>\r\n\u003Cli>Interrupt controller\u003C/li>\r\n\u003Cli>Memory mapped interrupts\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Firmware\r\n\u003Cul>\r\n\u003Cli>Booting\u003C/li>\r\n\u003Cli>UEFI overview\u003C/li>\r\n\u003Cli>ACPI overview\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>PCIe support\r\n\u003Cul>\r\n\u003Cli>Bridge to PCIe\u003C/li>\r\n\u003Cli>Interrupt delivery\u003C/li>\r\n\u003Cli>Configuration space\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Other topics\r\n\u003Cul>\r\n\u003Cli>Core power management, power controller\r\n\u003Cul>\r\n\u003Cli>Power modes (dormant, shutdown)\u003C/li>\r\n\u003Cli>WFI, WFE, SEV\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Server reliability features, ECC protection, error reporting\u003C/li>\r\n\u003Cli>Debug\u003C/li>\r\n\u003Cli>Linaro\u003C/li>\r\n\u003Cli>64-bit tool chain overview\u003C/li>\r\n\u003Cli>64-bit Linux overview\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cem>Optional Topics (Not covered in standard 4-day course)\u003C/em>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>32-bit v7 Architecture Overview (1-day)\r\n\u003Cul>\r\n\u003Cli>Overview of 32-bit v7 ISA (registers, instruction set, etc.)\u003C/li>\r\n\u003Cli>Memory and Paging architecture overview\u003C/li>\r\n\u003Cli>Interrupt handling and exception overview\u003C/li>\r\n\u003Cli>Floating Point, TrustZone and NEON overview\u003C/li>\r\n\u003Cli>Example 32-bit processor pipeline overview\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Additional 64-bit ISA material not covered in standard 4-day course (1 day)\u003C/li>\r\n\u003Cli>ARM processor virtualization support (1-day)\r\n\u003Cul>\r\n\u003Cli>Processor mode (Hyp mode, EL2) added in 32-bit ARM to implement hardware virtualization of the processor core\u003C/li>\r\n\u003Cli>The intersection of virtualization support and security support (TrustZone)\u003C/li>\r\n\u003Cli>ARM 64-bit processor virtualization implementation – Exception Levels 2 and 3\u003C/li>\r\n\u003Cli>Interrupts and Virtualization\u003C/li>\r\n\u003Cli>Memory management\u003C/li>\r\n\u003Cli>Paravirtualization techniques\u003C/li>\r\n\u003Cli>Hardware support for paging guest operating systems\u003C/li>\r\n\u003Cli>Significance of guest physical (intermediate physical address space), especially with regard to I/O\u003C/li>\r\n\u003Cli>The SMMU\u003C/li>\r\n\u003Cli>TLB management and TLB features to support virtualization\u003C/li>\r\n\u003Cli>IO Virtualization\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","https://mindshare-prod.s3.amazonaws.com/public/live_training_courses/thumbnails/live_training_course_713_thumbnail_1748360454.png",[19,46],{"id":20,"name":21,"slug":22,"description":23,"whats_included":24,"about":25,"instructor_fullname":26,"instructor_email":27,"equivelent_of":28,"subscription_length":29,"price":30,"price_arbor":30,"course_category_id":31,"elearning_courses":32,"you_will_learn":33,"prerequisites":34,"is_active":13,"modified_at":10,"order":35,"modules_count":36,"video":37},1720,"ARM 64-bit Architecture (ARM v8-A) eLearning Course","arm-64-bit-architecture-arm-v8-a-elearning-course","\u003Cp>This course covers the 64-bit ARMv8-A architecture that follows on from and offers compatibility with the earlier ARMv7-A 32-bit architecture. Examples of processors that first implemented this 64-bit architecture are the ARM Cortex-A53 and Cortex A57 processors. Since the successful introduction of the ARMv8-A architecture and products, there have been several architectural enhancements. \u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/armv8a_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/armv8a_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>ARMv8-A eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARMv8-A\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","Paul Devriendt","paul@mindshare.com",4,120,"895",5,[],"\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>ARM architecture (ARMv8-A)\u003C/li>\r\n\u003Cli>Support for execution of 32-bit ARMv7-A code\u003C/li>\r\n\u003Cli>64-bit ISA (registers, instruction set, system instructions, etc)\u003C/li>\r\n\u003Cli>Floating point and Neon\u003C/li>\r\n\u003Cli>Calling conventions\u003C/li>\r\n\u003Cli>Memory and paging\u003C/li>\r\n\u003Cli>Exception and Interrupt handling, and the exception levels\u003C/li>\r\n\u003Cli>Virtualization (Exception Level 2)\u003C/li>\r\n\u003Cli>TrustZone overview (Exception Level 3)\u003C/li>\r\n\u003Cli>Power management\u003C/li>\r\n\u003Cli>Debug\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","null",30,22,{"id":38,"local_path":39,"file_name":40,"mime":10,"vimeo_uri":41,"duration":42,"thumbnail_filename":43,"local_thumbnail_path":44,"thumbnail_url":45},37726,"storage/app/videos/legacy/previews/","legacy-417348333.mp4","/videos/417348333",0,"ARM_64-bit_Architecture_(ARM_v8-A)_eLearning_Course_thumbnail.png","storage/app/public/thumbnails/","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/ARM_64-bit_Architecture_%28ARM_v8-A%29_eLearning_Course_thumbnail.png",{"id":47,"name":48,"slug":49,"description":50,"whats_included":51,"about":52,"instructor_fullname":26,"instructor_email":27,"equivelent_of":53,"subscription_length":29,"price":54,"price_arbor":54,"course_category_id":31,"elearning_courses":55,"you_will_learn":56,"prerequisites":57,"is_active":13,"modified_at":10,"order":42,"modules_count":58,"video":59},1739,"Fundamentals of ARM Architecture eLearning Course","fundamentals-of-arm-architecture","\u003Cp>This fundamentals course is a great start for any hardware or software engineer looking to get a base understanding of the ARM architecture. Topics range from the ARM instruction sets, processor modes, architecture profiles, instruction pipelines, bus interfaces, software development environments and much more.\u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/armfund_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/armfund_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>ARM eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARM Architecture\" to Life for You\u003C/strong>\u003C/span>\u003C/p>",1,"195",[],"\u003Cul>\r\n\u003Cli>Variety of ARM processors\u003C/li>\r\n\u003Cli>Terminology\u003C/li>\r\n\u003Cli>32-bit and 64-bit architectures\u003C/li>\r\n\u003Cli>System buses\u003C/li>\r\n\u003Cli>Software development environment\u003C/li>\r\n\u003C/ul>","\u003Cp>None\u003C/p>",12,{"id":60,"local_path":39,"file_name":61,"mime":10,"vimeo_uri":62,"duration":42,"thumbnail_filename":63,"local_thumbnail_path":44,"thumbnail_url":64},37745,"legacy-417348530.mp4","/videos/417348530","Fundamentals_of_ARM_Architecture_thumbnail.png","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/Fundamentals_of_ARM_Architecture_thumbnail.png",[],[67,73],{"id":68,"course_name":6,"classroom_info":15,"virtual_classroom_info":69,"file_url":70,"course_link":71,"link":10,"file_name":72},210,"8 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_ARM_64bit_Server_Agenda.pdf","/live-training-course/arm-64-bit-server-architecture","MindShare_ARM_64bit_Server_Agenda.pdf",{"id":74,"course_name":75,"classroom_info":76,"virtual_classroom_info":77,"file_url":78,"course_link":79,"link":80,"file_name":81},155,"ARMv8-A and ARMv9-A 64-bit Architecture","4 or 5 days","8 or 10 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_ARMv8A_ARMv9A_64bit_Agenda.pdf","/live-training-course/arm-64-bit-architecture","/elearning-course/arm-64-bit-architecture-arm-v8-a-elearning-course","MindShare_ARMv8A_ARMv9A_64bit_Agenda.pdf",[10],1793108630062]