[{"data":1,"prerenderedAt":38},["ShallowReactive",2],{"GET-live-training-course/slug/hbm-{}-{}":3},{"data":4},{"id":5,"name":6,"slug":7,"description":8,"about":9,"training_materials":10,"you_will_learn":11,"prerequisites":12,"is_active":13,"category_id":14,"duration":15,"modified_at":16,"course_outline":17,"supplied_materials":16,"thumbnail":18,"elearning_courses":19,"ebooks":20,"topics":21,"reviews":37,"meta_title":16,"meta_description":16,"meta_keywords":16},746,"HBM - High Bandwidth Memory","hbm","\u003Cp>High Bandwidth Memory (HBM) is a form of DRAM used on the most capable HPC and SoC platforms. HBM is an evolution of WideIO and WideIO2 with some concepts borrowed from Graphics DRAM. HBM provides the maximum possible bandwidth of any DRAM technology, largely by implementing several very wide channels. All DRAM (PC DRAM, LP DRAM, Graphics DRAM, HBM) are very similar to one another, but there are significant differences in HBM that this course covers in detail up to and including HBM4E.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(186, 55, 42);\">\u003Cstrong>All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"HBM\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli>PDF of course slides\u003C/li>\r\n\u003Cli>HBM Architecture eLearning (when available)\u003C/li>\r\n\u003C/ul>","\u003Cul>\r\n\u003Cli>DRAM architecture fundamentals if you book a 4-Day class\u003C/li>\r\n\u003Cli>Where JEDEC expects HBM to be placed in a system\u003C/li>\r\n\u003Cli>Organization and operation of HBM devices\u003C/li>\r\n\u003Cli>Electrical characteristics of HBM and why HBM lacks many SI tools found in other technologies\u003C/li>\r\n\u003Cli>Differences between WideIO, WideIO2, HBM1, HBM2, HBM2E, HBM3, HBM3E, HBM4 and HBM4E\u003C/li>\r\n\u003Cli class=\"MsoNormal\">HBM3/HBM3E/HBM4/HBM4E bank state machine, commands and waveforms\u003C/li>\r\n\u003Cli class=\"MsoNormal\">Overview of IEEE 1500\u003C/li>\r\n\u003Cli class=\"MsoNormal\">Calibration and training of HBM channels\u003C/li>\r\n\u003Cli class=\"MsoNormal\">HBM power management\u003C/li>\r\n\u003Cli class=\"MsoNormal\">HBM error handling\u003C/li>\r\n\u003C/ul>","\u003Cp>Completion of MindShare’s Fundamentals of DRAM course or equivalent industry experience for a 3 Day class, otherwise for 4 Day class, digital design and computer architecture background.\u003C/p>",true,4,"3 - 4 days",null,"\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>DRAM Fundamentals (1 Day) - Day 1 can be skipped with DRAM fundamentals prerequisite knowledge\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cul>\r\n\u003Cli>System Architecture and Intro to DRAM\u003C/li>\r\n\u003Cli>DRAM Device Architecture\u003C/li>\r\n\u003Cli>Packaging and HBM\u003C/li>\r\n\u003Cli>DRAM Controller Basics and Addresses\u003C/li>\r\n\u003Cli>DDR4 Device and Pin Descriptions\u003C/li>\r\n\u003Cli>Signal Routing\u003C/li>\r\n\u003Cli>DDR4 - Bank State Machines, Commands and Waveforms\u003C/li>\r\n\u003Cli>Refresh\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>HBM Topics (3 Days)\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cul>\r\n\u003Cli>System Architecture and Packaging\r\n\u003Cul>\r\n\u003Cli>Example Platforms\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Channel Architecture, Device Organization and Device Architecture\r\n\u003Cul>\r\n\u003Cli>Features and Architectures of Previous Technologies (PC and LP DRAMs)\u003C/li>\r\n\u003Cli>HBM Channels and Pseudo channels\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Signal Descriptions\r\n\u003Cul>\r\n\u003Cli>Channel Signals\u003C/li>\r\n\u003Cli>Global Signals\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Bank State Machines, Commands and Waveforms\r\n\u003Cul>\r\n\u003Cli>Simultaneous Row and Column Commands\u003C/li>\r\n\u003Cli>Use of WDQS and RDQS\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Refresh\r\n\u003Cul>\r\n\u003Cli>Auto Refresh\u003C/li>\r\n\u003Cli>Self Refresh\u003C/li>\r\n\u003Cli>Single-bank (Per-bank) Refresh\u003C/li>\r\n\u003Cli>Row Hammer, Target Row Refresh and Refresh Management\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Electrical Specifications\r\n\u003Cul>\r\n\u003Cli>Why so many traditional SI tools (ODT, ZQ cal, etc.) are not present\u003C/li>\r\n\u003Cli>IDD Specification\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Power Management\r\n\u003Cul>\r\n\u003Cli>Power Down\u003C/li>\r\n\u003Cli>Clock Throttling\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Initialization, Calibration, and Training\r\n\u003Cul>\r\n\u003Cli>JEDEC Initialization\r\n\u003Cul>\r\n\u003Cli>Mode Registers\u003C/li>\r\n\u003Cli>Initialization Steps\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Calibration and Training\r\n\u003Cul>\r\n\u003Cli>Vref Training\u003C/li>\r\n\u003Cli>Loopback LFSR MISR Training\r\n\u003Cul>\r\n\u003Cli>Command Bus (AWORD) Training\u003C/li>\r\n\u003Cli>Data Group (DWORD) Training\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Duty Cycle Adjustment (DCA) and Duty Cycle Monitoring (DCM)\u003C/li>\r\n\u003Cli>WDQS Interval Oscillator\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Errors and Error Handling\r\n\u003Cul>\r\n\u003Cli>Temperature\u003C/li>\r\n\u003Cli>Address Parity\u003C/li>\r\n\u003Cli>Data Parity\u003C/li>\r\n\u003Cli>Lane Remapping\u003C/li>\r\n\u003Cli>Sideband ECC\u003C/li>\r\n\u003Cli>On-Die ECC\u003C/li>\r\n\u003Cli>Post Package Repair\r\n\u003Cul>\r\n\u003Cli>Self-Repair\u003C/li>\r\n\u003Cli>Hard and Soft Repair\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Overview of IEEE 1500\u003C/li>\r\n\u003C/ul>","https://mindshare-prod.s3.amazonaws.com/public/live_training_courses/thumbnails/live_training_course_746_thumbnail_1755651111.png",[],[],[22,30],{"id":23,"course_name":6,"classroom_info":24,"virtual_classroom_info":25,"file_url":26,"course_link":27,"link":28,"file_name":29},207,"4 days","8 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_HBM_Outline.pdf","/live-training-course/hbm","/elearning-course/hbm-elearning-course","MindShare_HBM_Outline.pdf",{"id":31,"course_name":32,"classroom_info":24,"virtual_classroom_info":25,"file_url":33,"course_link":34,"link":35,"file_name":36},179,"Modern DRAM (DDRx / LPDDRx)","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_Comprehensive_DRAM_DDR5_LPDDR6_Outline.pdf","/live-training-course/dram-ddr5lpddr5-architecture","/elearning-course/modern-dram-ddr5-ddr4-lpddr5-lpddr4-elearning-course","MindShare_Comprehensive_DRAM_DDR5_LPDDR6_Outline.pdf",[16],1793108628810]